Variable latency memory circuit

Details Variable latency memory circuit Variable latency memory circuit

1997-12-23

1999-10-12

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 365236, G11C 800

Patent

active

059663430

ABSTRACT:
A memory integrated circuit includes a memory cell array, data lines 211 for transferring data to and from the memory cell array, data storage circuitry 200 coupled between the memory cell array and the data lines, and programmable circuitry 202, 206, 208 coupled to the data storage circuitry and responsive to control inputs and a clock signal for releasing data in the data storage circuitry. In further embodiments, the data storage circuitry includes a latch and the programmable circuitry includes circuitry for counting a predetermined number of cycles of the clock signal prior to releasing data in the data storage circuitry. The integrated circuit may also include circuitry 302 for transferring data to or from said array in a burst comprising a plurality of data bits.

REFERENCES:
patent: 5386385 (1995-01-01), Stephens, Jr.
patent: 5729503 (1998-03-01), Manning
patent: 5802005 (1998-09-01), Nakamura et al.

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