Variable increment phase locked loop circuit

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 16, H03B 300

Patent

active

040577686

ABSTRACT:
A variable increment phase locked loop circuit designed for use in a digital data communications system wherein a data input signal is synchronized with a local feedback signal by means of comparing the data input signal and the local feedback signal, and providing frequency adjustments to the feedback signal that are proportional to the instantaneous deviation between the data input signal and the feedback signal. In one embodiment, the circuit is not responsive to deviations between the data input signal and the feedback signal that are less than a preset threshold value. The output of the circuit is useful as a stabilized system clock signal.

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patent: 3931585 (1976-01-01), Barker et al.
patent: 3956710 (1976-05-01), Seitz et al.
patent: 4001713 (1977-01-01), Egan

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