Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-10-10
2002-12-03
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S762000, C257S765000
Reexamination Certificate
active
06489683
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to electroplating of conductors used in semiconductors.
BACKGROUND ART
In the manufacturing of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by an electroplating of the conductive material on the seed layer in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper electroplating is a slow process, which means that manufacturing, throughput is relatively low.
Another drawback of using copper is that copper is subject to electromigration, which means that copper migrates under the influence of current flow. This means that areas where the current density is relatively high, such as in vias, there is a tendency to form voids. This tends to increase current density further which increases the size of the voids until open circuits occur.
Separate solutions for both problems have been long sought but have eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and vias, it is becoming more pressing that solutions be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel. This speeds up the overall manufacturing process while the fine grain structure increases electromigration resistance.
The present invention provides a method for forming conductive layers in semiconductor channels and vias by using ramped direct current for the electroplating process. This speeds up the overall manufacturing process and deposits a fine grain structure conductive layer which increases electromigration resistance.
The present invention provides a method for forming conductive layers in semiconductor channels and vias by using ramped forward pulse current for the electroplating process. This speeds up the overall manufacturing process and deposits a fine grain structure conductive layer which increases electromigration resistance.
The present invention provides a method for forming conductive layers in semiconductor channels and vias by using ramped reverse pulse current for the electroplating process. This speeds up the overall manufacturing process and deposits a fine grain structure conductive layer which increases electromigration resistance.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 3876389 (1975-04-01), Chaudhari et al.
patent: 5906725 (1999-05-01), Lin et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6024857 (2000-02-01), Reid
patent: 6074544 (2000-06-01), Reid et al.
patent: 6242349 (2001-06-01), Nogami et al.
patent: 6297157 (2001-10-01), Lopatin et al.
Iacoponi John A.
Lopatin Sergey D.
Advanced Micro Devices , Inc.
Ishimaru Mikio
Quach T. N.
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