Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
2001-05-18
2004-02-17
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S300000
Reexamination Certificate
active
06693492
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a low-noise variable gain amplifier utilizing variable degeneration to provide gain control.
BACKGROUND OF THE INVENTION
Low-noise variable gain amplifiers have a wide range of applications, one significant application is in solid state radio telephones. It is desirable to provide for a low-noise variable gain operation under a wide range of circumstances. In a common prior art environment, a transistor amplifier is utilized operating an amplifier transistor in the common emitter mode, with the emitter of the amplifier transistor connected to ground. Gain control is accomplished by bypassing the base-emitter circuit of the amplifier transistor with a field effect transistor (FET) or similar switch. The amplifier transistor is turned off by removing forward bias. If the emitter is connected to a true ground, the optimum noise figure for the amplifying transistor can be realized. However, once the switch is energized and the amplifying transistor is turned off, the output to input isolation of the amplifying transistor is drastically reduced. In the active state, the amplifying transistor output to input isolation is normally 30-40 dB, but the isolation drops to 5 decibels or less when the amplifying transistor is off, particularly in single stage low-noise amplifiers. It is therefore desirable to keep the amplifying transistor active, but with reduced gain.
A common prior art method of remedying this situation is to reduce the gain of the amplifying transistor by lowering the operating current. This, however, provides a significant disadvantage in that lowering the operating current also reduces the third order intercept point (IP3) of the amplifier. In other words, the dynamic range of the amplifier is reduced. A reduction in dynamic range is highly undesirable since the amplifier is normally required to handle increased input signal levels in the reduced gain mode.
One technique used to reduce the gain, stabilize and increase the dynamic range of amplifying transistors is degeneration. Degeneration comprises placing an unbiased resistor in the emitter-ground circuit. The larger the resistance, the more the gain is reduced. Degeneration, however, lifts the emitter off radio frequency ground and raises input impedance of the amplifier in proportion to the resistance. If the resistor were replaced by a substantially ideal device, an on-resistance of zero ohms at the frequency of the signal being amplified, zero inductance and an off-resistance of greater than 1000 ohms, operation would be highly satisfactory. However, devices idealized to this extent are not available.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a low-noise, variable gain amplifier maintaining satisfactory input-output isolation in a reduced gain mode. It is another general object of the present invention to retain dynamic range of the amplifier as gain is reduced. It is a further object of the present invention to provide degeneration in an amplifier maintaining satisfactory output characteristics while using non-ideal components to switch the emitter to ground circuit in a common emitter arrangement.
Briefly stated, in accordance with the present invention a degeneration circuit is provided in a variable gain, low-noise amplifier. The degeneration circuit does not require specific frequency determining elements or output matching networks. A degenerating device is connected between the emitter of the amplifying transistor and ground. A large junction field effect transistor is a suitable degeneration device because of its inherently low on-resistance and the low gain current required to switch its conductive state. A resistor connected across the FET switch provides a finite limit to the total resistance in the emitter circuit of the amplifying transistor. Additional circuitry may be provided in the emitter-base circuit of the amplifying transistor such as an impedance correcting circuit designed to compensate for changing base input impedance as the result of change in the resistance of the degeneration circuit.
REFERENCES:
patent: 5532471 (1996-07-01), Khorramabadi et al.
patent: 5708392 (1998-01-01), Gross
patent: 5710523 (1998-01-01), Kobayashi
patent: 6175279 (2001-01-01), Ciccarelli et al.
patent: 6181206 (2001-01-01), Palmisano et al.
Blakely , Sokoloff, Taylor & Zafman LLP
International Business Machines - Corporation
Nguyen Khanh Van
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