Variable gain low noise amplifier

Details Variable gain low noise amplifier Variable gain low noise amplifier

2003-04-16

2004-11-16

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including gain control means

C330S278000

Reexamination Certificate

active

06819179

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the control of the gain of amplifiers or other high frequency blocks such as filter attenuators etc., by switching the load impedance. The invention in particular relates to controlling the gain of a Low Noise Amplifier (LNA).
2. Description of the Related Art
The problem of gain control versus the noise figure (NF) of low noise amplifiers as frequencies go steadily higher in the Giga Hertz range is a continuing challenge to all workers in this field. We now describe a circuit of the related art by referring to FIG.
1
. FIG. 1 is taken from U.S. Pat. No. 6,046,640 (Brunner), discussed below, and is referred there to as FIG. 6. The circuit is a switched-gain cascode amplifier, including an input stage
26
, a loading network
24
, first and a second cascode transistors Q
22
, Q
23
, and a bias signal generator
22
. The input stage
26
receives a bias signal V
BIAS
and the input signal V
IN
. The loading network
24
is coupled to a power supply voltage V
CC
and provides an output signal V
OUT
to a load. The input to the base of the first cascode transistor is a gain control signal V
G
. The input to the base of the second cascode transistor is a base control signal V
BC
. As mentioned the load is connected to the loading network
24
which attenuates the output signal by a different amount depending on which input terminal the signal is switched to.
Listed below are related patents and a publication which bear on this problem:
U.S. Pat. No. 6,466,095 B1 (Susuki) dated Oct. 15, 2002, Power Amplifier:—relates to gain variation and power amplification, whereas our invention, described below, is for a low noise amplifier (LNA). Unlike the LNA, the Power Amplifier (PA) is a large signal block, i.e., it deals with higher signal power. The main performance criterion for a PA is efficiency while for the LNA the main performance criterion is the Noise Figure (NF). In addition, the circuit of the PA itself is different from the LNA. The PA gain control scheme is also entirely different and can not be applied to the LNA.
U.S. Pat. No. 6,392,492 B1 (Yuan) dated May 21, 2002, High Linearity Cascode Low Noise Amplifier, and
EP 0 977 352 A2 (Fong), Noise Figure and Linearity Improvement Technique using Shunt Feedback:—both patents are for LNAs and teach techniques to improve the Noise Figure and linearity of the LNA in its normal (High Gain) mode of operation, whereas our invention proposes a gain control circuit for the LNA. The proposed Variable Gain LNA achieves the best Noise Figure in the High Gain mode and best linearity (surely better than the achievable linearity of the quoted patents) in the Low Gain mode. In addition, the reduced gain in the Low Gain mode greatly reduces the linearity requirements of the following blocks like Mixers, Filters etc, resulting in a power-efficient overall receiver. Reduced gain also reduces the dynamic range of the AGC circuit, which helps to improve the Signal to Noise Ratio (SNR).
U.S. Pat. No. 6,046,640 (Brunner) dated Apr. 4, 2000, Switched-Gain Cascode Amplifier Using Loading Network for Gain Control:—this patent also is about Variable Gain LNAs. This circuit bypasses both AC and DC signals to ground in the Low Gain mode, whereas our proposed circuit bypasses only the AC signal to ground thereby not wasting the DC power. The main advantage of doing so in our scheme is that the Noise Figure and Linearity in the Low Gain mode is improved substantially. Also the input impedance is unaffected and the gain flatness is improved during gain variation. Another advantage is that one can get any amount of gain control with this circuit. Based on the requirement, the circuit can be optimized for the gain variation or the linearity or both in the Low Gain mode.
Related Publication: Gain Controllable Very Low Voltage (≦1 V) 8-9 GHz Integrated CMOS LNA's, T. K. K. Tsang and M. N. El-Gamal,”
IEEE RFIC Symposium
2002. The scheme proposed in this publication controls the gate bias of the PMOS transistor in the folded cascode topology and does not sacrifice the NF in Low Gain mode. A parallel tank circuit is used from VDD to the amplifier which needs lots of care to achieve in a commercially packaged LNA. The gain control scheme which we propose not only achieves a better NF but also a superior third order intercept point (IIP3) in the Low Gain mode.
SUMMARY OF THE INVENTION
It is an object of at least one embodiment of the present invention to provide a circuit and a method where the load of the cascode amplifier is varied by connecting another (secondary) load in parallel with the original load through a switch which also acts as a voltage controlled resistor.
It is another object of the present invention to provide a number of such switchable loads which are connected across the load to obtain programmability of the gain.
It is yet another object of the present invention to vary the load impedance as a function of a control voltage.
It is still another object of the present invention to improve the noise figure and to reduce the linearity requirements in low gain mode.
It is a further object of the present invention to use the bias current effectively in the low gain mode.
These and many other objects have been achieved by connecting a secondary load through a MOSFET switch. During the High Gain Mode the MOSFET switch is OFF and the secondary load is electrically isolated from the main load, whereas in the Low Gain Mode the switch is turned ON and the secondary load appears across the primary load, thereby reducing the effective load impedance. The secondary load is AC coupled such that the DC bias current does not pass through the secondary load and hence the Noise Figure (NF) and linearity (IIP3) performance are better in the Low Gain Mode.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 6046640 (2000-04-01), Brunner
patent: 6184751 (2001-02-01), Siomkos et al.
patent: 6366166 (2002-04-01), Belot
patent: 6392492 (2002-05-01), Yuan
patent: 6424222 (2002-07-01), Jeong et al.
patent: 6438364 (2002-08-01), Waite
patent: 6466095 (2002-10-01), Suzuki
patent: 2003/0067359 (2003-04-01), Darabi et al.
patent: 0977352 (2000-02-01), None
Tommy K.K. Tsang et al., “Gain Controllable Very Low Voltage (≲1 V) 8-9 GHz Integrated CMOS LNA's,” 2002.
IEEE Radio Frequency Integrated Circuits Symposium pp. 205-208.

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