Variable gain circuit

Details Variable gain circuit Variable gain circuit

2000-10-27

2003-05-13

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S285000

Reexamination Certificate

active

06563383

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-306798, filed Oct. 28, 1999; and No. 2000-284708, filed Sep. 20, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a variable gain circuit which is used for a portable radio transceiver or the like to linearly change the gain displayed in decibels (dB) in accordance with a gain control signal.
Recently, mobile communication facilities typified by portable telephones have been vigorously developed. These communication facilities are carried by users and mounted on automobiles and the like when they are used, and hence required to be reduced in size and weight. It is therefore strongly desired that the components of such a radio device be implemented in monolithic IC (Integrated Circuit) form suited for reductions in size and weight rather than being implemented in hybrid form having many components connected to each other as in the prior art.
There have been demands for a reduction in the cost of radio devices as well as a reduction in the size of components. The IC technology is also effective for a reduction in the cost of radio devices.
In addition, transmission power control is indispensable to CDMA (Code Division Multiple Access) radio transceivers that have been increasingly developed in recent years. Under certain circumstances, therefore, a transmission IF (Intermediate Frequency) variable gain circuit is required to perform signal level control on 70 dB or higher. In general, to perform such high-level gain control, the gain displayed in decibels is required to be linearly adjusted in accordance with a gain control signal. This operation is required to facilitate gain control.
FIG. 16
is a circuit diagram of a conventional variable gain circuit using bipolar transistors. This variable gain circuit is comprised of a variable gain amplifier
1
and a control signal compensation circuit
2
. Bipolar transistors Q
1
and Q
2
constitute a differential pair. An IF signal (input current Isig) is input to the common emitter terminal. An output current Ia is extracted from the collector terminal of the bipolar transistor Q
1
. To generate the output current Ia from an input current Isig, a gain control signal V
z1
is input between the base terminals of the bipolar transistors Q
1
and Q
2
. Note that the arrows in
FIG. 16
indicate the directions of currents.
A current Isig-Ia flowing in the collector of the bipolar transistor Q
2
is regarded as an unwanted current and designed to flow in a power supply (not shown) or the like. In this case, a transfer function from Isig to Ia is represented by
I
a
I
sig
=
1
1
+
exp
⁡
(
V
z1
V
T
)
(
1
)
where V
T
is the thermal voltage, which is about 26 mV at room temperature.
According to equation (1), under the condition of 1<<exp(V
z1
/V
T
), the transfer function can be approximated by Ia/Isig=1/exp(V
z1
/V
T
). Obviously, as the gain control signal V
z1
increases, the gain (Ia/Isig) exponentially decreases.
If the above hypothesis (1<<exp(V
z1
/V
T
)) does not hold, the relationship between the gain control signal V
z1
and the gain (Ia/Isig) deviates from an exponential relationship. That is, if the hypothesis of 1<<exp(V
z1
/V
T
) does not hold with respect to the gain control signal V
z1
, the relationship between the gain (Ia/Isig) displayed in decibels and the gain control signal V
z1
becomes nonlinear. For this reason, there is proposed a variable gain circuit whose gain (Ia/Isig) decreases exponentially with respect to an internal gain control signal Vx by using a gain control signal compensation circuit
2
comprised of the bipolar transistors Q
10
and Q
11
, a current source Io, a voltage source V
BB
, and a gain control current source I
1
=Io·exp(−b·Vx) for gain correction [see Japanese Patent Application No. 10-370290 (Jpn. Pat. Appln. KOKAI Publication No. 2000-196386) as the specification of a previous application]. When this gain control signal compensation circuit
2
is used, the gain control signal Vx and gain (Ia/Isig) are given by
I
a
I
sig
=
exp
⁡
(
-
b
·
V
x
)
(
2
)
where b is a constant, which is 2 to 4, for example.
FIG. 17A
is a block diagram of a conventional variable gain circuit using bipolar transistors.
FIG. 17B
is a graph showing the relationship between an external gain control signal Vc supplied from the outside of the variable gain circuit and a voltage gain GAIN (Vout/Vin) (dB). Reference symbol (dB) denotes a gain displayed in decibels; ditto for the following description. In this case, the external gain control signal Vc is equal to the internal gain control signal Vx, and Isig=g
1
·Vin and Ia=g
2
·Vout, where g
1
and g
2
are the conductance, which is, for example, 0.1(A/V).
By using the block arrangement shown in
FIG. 17A
, the internal gain control signal Vx and gain (Ia/Isig) have an exponential relationship. However, this relationship holds only when bipolar transistors are used.
More specifically, if the variable gain circuit in
FIG. 16
is formed by using field-effect transistors (FETs), the internal gain control signal Vx and gain (Ia/Isig) cease to have an exponential relationship. This problem will be described in detail below.
Note that the following FETs indicate n-type (n-channel) MOS transistors (MOSFETS) unless otherwise specified.
FIG. 18
shows the variable gain circuit in
FIG. 16
which is formed by using MOSFETS, assuming that FETs are MOSFETS. In this case, with the use of the internal gain control signal V
x
, I
D1
is given by
I
D1
=I
o
·exp(−
b·V
x
)  (3)
where Io is the current value of a constant current source, and b is a constant. Referring to
FIG. 18
, I
D2
=Io−I
D1
holds. When this circuit is designed so that the current densities of the transistors M
1
and M
2
equal to those of the transistors M
10
and M
11
, a current gain GMOS (=Iout
1
/Isig
1
) of a variable gain amplifier
11
is given by
G
MOS
=
gm
11
gm
11
+
gm
10
=
gm
1
gm
1
+
gm
2
(
4
)
where gm
1
, gm
2
, gm
10
and gm
11
are the transconductance of MOS transistors M
1
, M
2
, M
10
and M
11
. Assuming that each of the transistors M
10
and M
11
exhibits a square characteristic which is a characteristic in a strong inversion, the relationships between currents I
D10
and I
D11
and gate voltages V
GS10
and V
GS11
are expressed as
I
D10
=&bgr;(
V
GS10
−V
TH
)
2
  (5)
I
D11
=&bgr;(
V
GS11
−V
TH
)
2
  (6)
where I
D10
is the drain current of the transistor M
10
, I
D11
is the drain current of the transistor M
11
, V
GS10
is the gate-to-source voltage of the transistor M
10
, V
GS11
is the gate-to-source voltage of the transistor M
11
, &bgr; is &mgr;·Cox·W/(2L), &mgr; is the mobility of carriers, Cox is the oxide film capacitance per unit area, W is the channel width, L is the channel length, and V
TH
is the threshold voltage. From equations (4), (5), and (6), G
MOS
is given by
G
MOS
=
2
⁢
β
·
I
D1
2
⁢
(
β
·
I
D1
+
⁢
β
·
I
D2
)
(
7
)
 
⁢
=
I
D1
I
o
+
2
⁢
I
D1
·
I
D2
(
8
)
 
⁢
=
I
o
·
exp
⁡
(
-
b
·
V
x
)
I
o
+
2
⁢
I
D1
·
I
D2
(
9
)
According to equation (9), if I
D1
>>I
D2
or I
D1
<<I
D2
, the denominator in the root in the equation (9) can be approximated by Io. Equation (9) can therefore be rewritten as:
G
MOS
={square root over (exp(−
b·V
x
))}  (10)
It is obvious from equations (10) and (2) that the relationship between the gain (dB) and the internal gain control signal Vx in the case where MOSFETs are used gradually approaches a straight line with a half slope as compared with the case where bipolar transistors are used.
If I
D1
=I
D2
=Io/2, i.e., V
z1
=0, since the denominator in the root in equation (9)

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