Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-08-13
2004-03-23
Callahan, Timothy P. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000, C330S278000, C330S285000, C327S052000
Reexamination Certificate
active
06710659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable-gain amplifier, i.e., an amplifier that permits its gain to be controlled, for use in an integrated circuit, and more particularly to a variable-gain amplifier for use in an integrated circuit for receiving digital satellite broadcasts.
2. Description of the Prior Art
FIG. 16
shows an example of the configuration of a conventional variable-gain amplifier. An input voltage signal V
IN1
is fed to a terminal that is connected to the base of an NPN-type input transistor Q
1
, and an input voltage signal V
IN2
is fed to a terminal that is connected to the base of an NPN-type input transistor Q
2
. The emitters of the input transistors Q
1
and Q
2
are connected together through a resistor RE
1
. The emitter of the input transistor Q
1
is grounded through a constant current source
1
that outputs a constant current I
C
, and the emitter of the input transistor Q
2
is grounded through a constant current source
2
that outputs a constant current I
C
.
To the collector of the input transistor Q
1
, the emitters of NPN-type transistors Q
3
and Q
4
are connected. To the collector of the input transistor Q
2
, the emitters of NPN-type transistors Q
5
and Q
6
are connected.
A constant voltage V
CC
is supplied to a terminal that is connected to one end of a resistor RL
1
, to the collector of the transistor Q
4
, to the collector of the transistor Q
5
, and to one end of a resistor RL
2
. The other end of the resistor RL
1
is connected to the collector of the transistor Q
3
and to a terminal from which an output voltage signal V
OUT1
is fed out, and the other end of the resistor RL
2
is connected to the collector of the transistor Q
6
and to a terminal from which an output voltage signal V
OUT2
is fed out.
A reference voltage V
B1
is supplied to a terminal that is connected to the base of the transistor Q
3
and to the base of the transistor Q
6
. A control voltage V
C1
is supplied to a terminal that is connected to the base of the transistor Q
4
and to the base of the transistor Q
5
.
Next, the operation of the variable-gain amplifier of
FIG. 16
will be described. When the levels of the input voltage signals V
IN1
and V
IN2
are low, the control voltage V
C1
is reduced so that the base potential of the transistors Q
3
and Q
6
is higher than the base potential of the transistors Q
4
and Q
5
. As a result, almost no current flows through the transistors Q
4
and Q
5
, and most of the collector current of the input transistors flows through the transistors Q
3
and Q
6
. Accordingly, a large amount of current flows through the output load resistors RL
1
and RL
2
, yielding a high gain.
On the other hand, when the levels of the input voltage signals V
IN1
and V
IN2
are high, the control voltage V
C1
is increased so that the base potential of the transistors Q
3
and Q
6
is lower than the base potential of the transistors Q
4
and Q
5
. As a result, most of the collector current of the input transistors flows through the transistors Q
4
and Q
5
, and almost no current flows through the transistors Q
3
and Q
6
. Accordingly, a small amount of current flows through the output load resistors RL
1
and RL
2
, yielding a low gain. Thus, the gain characteristic curve T
1
of the variable-gain amplifier of
FIG. 16
with respect to the control voltage V
C1
is as shown in FIG.
17
. In
FIG. 17
, the symbol V
th1
represents the threshold level of the control voltage V
C1
at which the variable-gain amplifier of
FIG. 16
starts attenuating its gain.
When the variable-gain amplifier is used in a digital satellite broadcast system or terrestrial broadcast system, the input voltage signals V
IN1
and V
IN2
are high-frequency signals having frequencies of from about a few hundred MHz to a few GHz. Moreover, in a digital satellite broadcast system or terrestrial broadcast system, a wide dynamic range of typically 60 dB or over is required.
However, in the variable-gain amplifier of
FIG. 16
, when high-frequency signals are fed in, leak current flows through the collector-emitter parasitic capacitance (about a few tens of fF) of the transistors Q
3
and Q
6
. This causes saturation of gain attenuation, and thus the gain characteristic curve T
2
of the variable-gain amplifier with respect to the control voltage V
C1
when high-frequency signals are fed in is as shown in FIG.
18
.
In this way, the variable-gain amplifier of
FIG. 16
cannot attenuate its gain sufficiently when high-frequency signals are fed in, and thus, quite inconveniently, does not offer a wide input dynamic range as required in a digital satellite broadcast system or terrestrial broadcast system.
FIG. 19
shows another example of the configuration of a conventional variable-gain amplifier. The variable-gain amplifier of
FIG. 19
is provided with a variable-gain amplifier circuit A
1
and a variable-gain amplifier circuit A
2
.
First, the configuration of the variable-gain amplifier circuit A
1
will be described. An input signal V
in1
is fed to a terminal that is connected to the base of an NPN-type input transistor Q
21
, and an input signal V
in2
is fed to a terminal that is connected to the base of an NPN-type input transistor Q
22
. The emitters of the input transistors Q
21
and Q
22
are connected together through a resistor R
7
. The emitter of the input transistor Q
21
is grounded through a constant current source
21
that produces a bias current I
C
, and the emitter of the input transistor Q
22
is grounded through a constant current source
22
that produces a bias current I
C
.
To the collector of the input transistor Q
21
, the emitters of NPN-type transistors Q
14
and Q
15
are connected. To the collector of the input transistor Q
22
, the emitters of NPN-type transistors Q
16
and Q
17
are connected.
A constant voltage V
CC
is supplied to a terminal that is connected to the collectors of the transistors Q
15
and Q
16
.
A bias voltage V
bias
is supplied to a terminal that is connected to the bases of the transistors Q
14
and Q
17
. A control voltage V
AGC
, which is a reference control voltage, is supplied to a terminal that is connected to the bases of the transistors Q
15
and Q
16
.
Next, the configuration of the variable-gain amplifier circuit A
2
will be described. The terminal to which the input signal V
in1
is fed is connected to the base of an NPN-type input transistor Q
20
, and the terminal to which the input signal V
in2
is fed is connected to the base of an NPN-type input transistor Q
23
. The emitters of the input transistors Q
20
and Q
23
are connected together through a resistor R
8
. The emitter of the input transistor Q
20
is grounded through a constant current source
20
that produces a bias current I
C
, and the emitter of the input transistor Q
23
is grounded through a constant current source
23
that produces a bias current I
C
.
To the collector of the input transistor Q
20
, the emitters of NPN-type transistors Q
12
and Q
13
are connected. To the collector of the input transistor Q
23
, the emitters of NPN-type transistors Q
18
and Q
19
are connected.
The terminal to which the constant voltage V
CC
is supplied is connected to one end of an output load resistor R
5
, to the collector of the transistor Q
13
, to the collector of the transistor Q
18
, and to one end of an output load resistor R
6
. The other end of the output load resistor R
5
is connected to the collector of the transistor Q
12
, and the other end of the output load resistor R
6
is connected to the collector of the input transistor Q
19
.
The terminal to which the bias voltage V
bias
is supplied is connected to the bases of the transistors Q
12
and Q
19
. The terminal to which the control voltage V
AGC
is supplied is connected through a resistor R
3
to the bases of the transistors Q
13
and Q
18
. The node between the resistor R
3
and the transistors Q
3
and Q
8
is grounded through a resistor R
4
.
The variable-gain amplifier circuits A
1
and A
2
configured as desc
Shimoda Mamoru
Teramoto Makoto
Birch & Stewart Kolasch & Birch, LLP
Callahan Timothy P.
Luu An T.
Sharp Kabushiki Kaisha
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