Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
1999-07-16
2001-04-03
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S098000, C330S284000
Reexamination Certificate
active
06211737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to gain control amplifier circuits and, more particularly, to a feedback technique which improves the linearity when switching from a high gain mode to one or more lower gain modes.
2. Description of the Prior Art
Variable gain amplifiers (“VGA's”) are used in numerous electronic products such as global positioning (GPS) receivers, wireless local area networks and mobile communication devices, such as cordless and cellular phones. In particular, VGA's are used in the various parts of such devices, for example, in the radio frequency (RF) input stage, intermediate frequency (IF) and low frequency or baseband circuits of these devices.
The linearity of a circuit may be defined by various parameters. For example, the input third-order intercept point represents third-order non-linearity in the transfer function of a circuit. Due to the third-order non-linearity, two undesired signals in adjacent channels generate output third-order intermodulation products (IM
3
) which can corrupt the desired signal at the output. The power of the desired signal at the output of a linear circuit increases linearly with the input power of the circuit. However, the power of the output IM
3
increases with the cube of the input power. The input third-order intercept point is the input power level, at which the power of the desired signal at the output of a circuit is equal to the power of the output IM
3
.
FIG. 1
shows a typical low-noise amplifier (LNA)
10
for amplifying input signals, such as radio-frequency signals propagating through receiving circuitry of a wireless system, such as a cellular telephone. A signal input RF
in
is provided for receiving an input signal from a source, such as a tuner or the previous amplifier stage. The input signal is supplied to the base of an NPN junction transistor Q
1
. A degeneration impedance Ze is coupled between the emitter of the transistor Q
1
and a ground terminal. The transistor Q
1
and the impedance Ze function as a common-emitter transconductance stage.
An NPN junction transistor Q
2
is connected to the transistor Q
1
in a cascode configuration. The emitter of the transistor Q
2
is connected to the collector of the transistor Q
1
. The base of the transistor Q
2
is supplied with bias voltage from a bias circuit which can be either on chip or off chip. A resistor R
1
and an inductor L
1
are coupled between the collector of the transistor Q
2
and a source of collector voltage Vcc. A capacitor C
1
is arranged between the collector of the transistor Q
2
and an output RF
out
of the low noise amplifier
10
.
The resistor R
1
is an output-matching resistor that functions to match the output impedance of the low noise amplifier
10
with the impedance of a load coupled to the output RF
out
. The inductor L
1
and capacitor C
1
form an impedance transformation network that transforms the output impedance defined by the resistor R
1
to match the impedance of the load. The inductor L
1
also serves as a pull-up inductor that increases the allowable voltage at the collector of the transistor Q
2
.
The gain of the amplifier of
FIG. 1
is controlled in discrete steps by using a well-known current dividing or splitting technique. A switch in the form of an NPN transistor Q
3
having its emitter coupled to the collector of the transconductance device Q
1
and its collector coupled to the power supply Vcc is provided with a control signal at its base B to render the switch conductive or non-conductive. When the switch Q
3
is in the non-conductive state, the amplifier is in the high gain mode and all of the current from the transconductance stage is delivered to the output RF
out
. When the switch Q
3
is conductive, the amplifier is in a reduced gain mode, as current is diverted from the output and dumped to the power supply by the switch Q
3
, thereby reducing the gain at the output RF
out
relative to the input RF
in
. In other words, current from the transistor Q
2
is split into two paths, with some of the current diverted through the transistor Q
3
and the remaining current provided to the output. In this current splitting technique, the gain step between the two gain modes depends on the device size ratios between the transistors Q
2
and Q
3
(with all emitters connected to the same node). This gain control scheme can be expanded by connecting additional transistors in parallel with transistors Q
2
and Q
3
(with all emitters connected to the same node).
A disadvantage of the gain control scheme of
FIG. 1
is that the VGA has the same linearity in both high and lower gain modes. In many applications, the VGA is required to have higher linearity when the VGA is switched from the high to the lower gain modes. When the VGA is switched to lower gain modes, it is typically because of higher input signal power, so increased linearity is desired.
It would be desirable to create a new technique that improves the linearity of a VGA when it is switched from a high gain mode to a lower gain mode.
SUMMARY OF THE INVENTION
Various advantages of the invention are achieved at least in part by providing an electronic circuit, such as an amplifier, which includes: (i) a transconductance stage which converts an input signal power into a signal current and supplies the current to an output of the circuit, (ii) a current diverting circuit branch coupled to selectively divert the current from the transconductance stage away from the output and (iii) a feedback network which feeds back a portion of the current diverted away from the output to the input of the transconductance stage. When implemented as a variable gain amplifier, the current diverting branch functions to change a gain of the circuit from a high level to one or more lower levels.
The invention is based in part on the recognition that in known VGA's as discussed with reference to
FIG. 1
, the linearity of the VGA is dominated by the linearity of the transconductance stage. The feeding back of a portion of the diverted current to the input improves the linearity of the circuit in the lower gain mode(s). Furthermore, since the feedback network does not couple the output to the input, the isolation of the output relative to the input is not compromised.
In accordance with one aspect of the present invention, the transconductance stage includes a first transistor having a control terminal, such as the base of a bipolar transistor or the gate of a MOS transistor, coupled to receive the input signal. A degeneration impedance may be provided between a main current electrode, such as an emitter or source, of the first transistor and a ground terminal.
According to another aspect of the invention, the current diverting branch includes a switching transistor which receives a bias voltage to control the conductance of the switch and thereby the diversion of current through said current diverting branch. The circuit may include a plurality of current diverting branches to implement an amplifier having several gain modes. The circuit may have more than one feedback network in dependence on the number of gain modes for which improved linearity is desired.
According to yet another aspect of the invention, the feedback network includes an impedance network coupled between an output terminal of the switching transistor of the current diverting branch and the input of the transconductance stage. The invention also concerns a method of feeding back a portion of current diverted from the output of a variable gain amplifier to improve the linearity of one or more gain modes.
These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings.
REFERENCES:
patent: 3512096 (1970-05-01), Nagata et al.
patent: 3892983 (1975-07-01), Okada et al.
patent: 4011519 (1977-03-01), Kawamura et al.
patent: 4021749 (1977-05-01), Ishigaki et al.
patent: 5047731 (1991-09-01), Lee
patent: 5323123 (1994-06-01), Philippe
Philips Electronics North America Corporation
Shingleton Michael B
Wieghaus Brian J.
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