Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2003-03-10
2004-09-14
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000
Reexamination Certificate
active
06791413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to variable gain amplifiers and particularly to linear gain amplifiers.
2. Description of the Background Art
FIG. 5
shows a variable gain amplifier configured of an amplification circuit
100
and a control circuit
400
controlling a gain of amplification circuit
100
. Amplification circuit
100
is configured, as described hereinafter. Amplification circuit
100
includes n-channel MOS transistors M
1
-M
6
(first to sixth MOS transistors, respectively), and load resistances Z1 and Z2 (first and second load resistances, respectively). Herein, transistors M
1
and M
2
are identical in characteristics, and so are transistors M
3
and M
4
, and transistors M
5
and M
6
. Herein, “identical in characteristics” means “equal in threshold voltage, gain constant, transconductance provided when a uniform current flows, and in drain resistance.”
Transistors M
3
and M
5
have their respective drains connected together at a point connected to a first output terminal. Transistors M
4
and M
6
have their respective drains connected together at a point connected to a second output terminal. Transistors M
3
and M
4
have their respective sources connected together at a point connected to transistor M
2
at the drain.
Transistors M
5
and M
6
have their respective sources connected together at a point connected to transistor M
1
at the drain.
Transistor M
1
is provided with a gate terminal Vc
1
connected to control circuit
400
and has its source connected to a first fixed potential (a ground potential). Transistor M
2
is provided with a gate terminal Vc
2
connected to control circuit
400
and has its source connected to the first fixed potential (the ground potential).
Transistor M
3
has its gate connected to its drain. Transistor M
4
has its gate connected to its drain. Transistor M
6
has its gate connected to a first input terminal IN
1
. Transistor M
5
has its gate connected to a second input terminal IN
2
.
Resistance Z1 has one end connected to a second fixed potential Vdd and the other end to a first output terminal OUT
1
. Resistance Z2 has one end connected to the second fixed potential Vdd and the other end to a second output terminal OUT
2
.
Input terminals IN
1
and IN
2
have potentials Vin− and Vin+, respectively, and output terminals OUT
1
and OUT
2
have potentials Vout+ and Vout−, respectively, and transistors M
1
and M
2
pass currents I1 and I2, respectively, for the sake of illustration.
FIG. 6
shows a circuit equivalent to the amplification circuit. In the figure, gm1 represents transconductance of transistors M
5
and M
6
, gm2 represents transconductance of transistors M
3
and M
4
, rd1 represents drain resistance of transistors M
5
and M
6
, rd2 represents drain resistance of transistors M
3
and M
4
, and Z represents resistance of load resistances Z1 and Z2. From this figure, the amplification circuit has a gain gain, as represented by the following equation:
gain
=
&LeftBracketingBar;
(
(
Vout
+
-
Vout
-
)
(
Vin
+
-
Vin
-
)
)
&RightBracketingBar;
=
g
m
1
·
(
rd
1
//
rd
2
//
1
gm
2
//
Z
)
,
(
A1
)
wherein // indicates an operation performed to calculate combined resistance of parallel connection. If rd1, rd2>>1/gm2, Z then gain is approximated, as follows:
gain
≅
gm
1
·
(
1
gm
2
//
Z
)
=
gm
1
·
(
Z
gm
2
Z
+
1
gm
2
)
=
gm
1
gm
2
·
1
1
Z
·
gm
2
+
1
.
(
A2
)
If &mgr;
n
represents an average surface mobility, Cox represents a gate capacitance per unit area, (W/L)
1
represents a channel width/a channel length of transistors M
5
and M
6
, and (W/L)
2
represents a channel width/a channel length of transistors M
3
and M
4
, then gm1 and gm2 are represented by the following equations:
gm
1
=
UnCox
(
W
L
)
1
·
I
1
(
A3
)
gm
2
=
UnCox
(
W
L
)
2
·
I
2
.
(
A4
)
By substituting expressions A3 and A4 into expression A2, the following expression:
gain
≅
UnCox
(
W
L
)
1
·
I
1
UnCox
(
W
L
)
2
·
I
2
×
1
1
Z
UnCox
(
W
L
)
2
·
I
2
(
A5
)
is obtained.
From expression A5, if Z is sufficiently large, then an expression:
gain ∝(I1/I2)
0.5
(A6)
is provided and gain is proportional to a square root of a ratio of current I1 to current I2.
Control circuit
400
is configured, as described hereinafter. Control circuit
400
includes p-channel MOS transistors M
21
and M
22
, n-channel MOS transistors M
11
and M
12
, and a constant current source Ibias1. Herein, transistors M
11
and M
12
are identical in characteristics, and so are transistors M
21
and M
22
.
Constant current source Ibias1 outputs a constant current Ibs1.
Transistors M
21
has its source connected to constant current source Ibias1, its drain connected to transistor M
11
at the drain, and its gate receiving a control voltage Vcon1.
Transistor M
22
has its source connected to constant current source Ibias1, its drain connected to transistor M
12
at the drain, and its gate receiving a control voltage Vcon2.
Transistor M
11
has its source connected to a first fixed potential (a ground potential), its drain connected to its gate and transistor M
21
at the drain, and gate terminal Vc
1
connected to gate terminal Vc
1
of transistor M
1
of amplification circuit
100
.
Transistor M
12
has its source connected to the first fixed potential (the ground potential), its drain to its gate and transistor M
22
at the drain, and gate terminal Vc
2
to gate terminal Vc
2
of transistor M
2
of amplification circuit
100
.
Constant current source Ibias1 has one end connected to a second fixed potential Vdd and the other end to transistors M
21
and M
22
at their respective sources.
Control circuit
400
operates, as described hereinafter. Transistors M
21
and M
22
are provided with a gain constant K and a threshold voltage Vth for the sake of illustration. Transistors M
21
and M
22
pass currents Id1 and Id2, respectively, and their respective gate-source voltages are represented as Vgs1 and Vgs2, respectively, for the sake of illustration. Currents Id1 and Id2 are represented by the following equations:
Ibs
1=
Id
1+
Id
2 (A7)
Id
1=
K×
(
Vgs
1
−Vth
)
2
(A8)
Id
2=
K×
(
Vgs
2
−Vth
)
2
(A9).
Herein, if a point S has a potential Vs then the following equations:
Vgs
1
=Vcon
1
−Vs
(A10)
Vgs
2
=Vcon
2
−Vs
(A11)
are established.
Herein, if
Vcon=Vcon
2
−Vcon
1 (A12)
then from expressions A7-A12 the following expressions:
{square root over (K)} Vcon={square root over (Ibs
1−
Id
1)}−
{square root over (Id1)}
(A13)
={square root over (Id2)}
−Ibs
1−
{square root over (Id2)}
(A14)
are obtained.
Expressions A13 and A14 are transformed to obtain the following two expressions:
Id
1
=
1
2
[
Ibs
1
+
2
Ibs
1
·
K
-
(
K
·
Vcon
)
2
·
Vcon
]
(
A15
)
Id
2
=
1
2
[
Ibs
1
-
2
Ibs
1
·
K
-
(
K
·
Vcon
)
2
·
Vcon
]
.
(
A16
)
FIG. 7
represents a relationship between Vcon, and Id1 and Id2. As shown in the figure, in a vicinity of Vcon=0, Id1 is directly proportional to Vcon and Id2 is directly proportional to −Vcon.
If
A
=
1
2
Ibs
1
(
A17
)
B
=
1
2
2
Ibs
&em
Hosoda Kinya
Hyogo Akira
Komurasaki Hiroshi
Satoh Hisayasu
Sekine Keitaro
Burns Doane Swecker & Mathis L.L.P.
Choe Henry
Renesas Technology Corp.
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