Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-11-04
2004-03-30
Van, Nguyen Khanh (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S278000
Reexamination Certificate
active
06714075
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a variable gain amplifier and a filter circuit, and more particularly, to a single-input multi-output variable gain amplifier and a filter circuit provided with the same.
Read channel systems for DVDs and the like use a technology of shaping the waveform of a raw signal from a disc to read the signal correctly. The waveform shaping is often realized by adjusting the zero position of a filter. Therefore, a filter for waveform shaping used in read channel systems is required to have an adaptive waveform shaping function that permits waveform shaping optimum for each signal from a disc. To attain adaptive waveform shaping, the filter must have an adjusting function of rendering the zero position variable.
FIG. 10
is a block diagram of a conventional second-order bi-quad GMC filter capable of adjusting the zero position. The bi-quad GMC filter of
FIG. 10
includes transconductors
71
and
72
, capacitors
73
and
74
and amplifiers
75
and
76
. The amplifiers
75
and
76
are provided for adjusting the zero position. The amplifier
75
outputs an input signal Vin to the transconductor
71
as it is (×1) without amplification. The amplifier
76
amplifies the input signal Vin by A times (×A) and outputs the amplified signal to the transconductor
72
. The transfer function of the GMC filter of
FIG. 10
is represented by expression:
V
out
V
in
=
gm
(
gm
+
sC1A
)
gm
2
+
sC1gm
+
s
2
C2C1
(
1
)
where C
1
and C
2
are the capacitances of the capacitors
73
and
74
, respectively, Vout is the output of the filter, and s is a Laplace variable. The zero position of the filter is represented by:
gm/(C
1
×A).
It is therefore found that the zero position of the filter can be adjusted by adjusting the gain A of the amplifier
76
.
The above description is for generation of the first-order zero. For generation of a second- or higher-order zero, the same bi-quad GMC filters as that of
FIG. 10
may be connected sequentially.
The amplifiers
75
and
76
used in the GMC filter of
FIG. 10
are required to have ideal characteristics of being small in deterioration of the phase rotation and gain within the band of the filter, and thus, high-speed operation is necessary. To fulfill this requirement, the power consumption and circuit area of the amplifiers
75
and
76
tend to be large.
The input signal Vin to the filter is branched by the amplifiers
75
and
76
, and the branched signals are input into the transconductors
71
and
72
. It is desirable that the difference in delay time between the signal from the amplifier
75
and the signal from the amplifier
76
is zero idealistically. If there is a delay time difference between these signals, the transfer function will fail to have a form as represented by expression (1), and the characteristics will be deviated from the idealistic characteristics. In particular, the group delay characteristic will be deviated enormously. Since the amplifiers
75
and
76
shown in
FIG. 10
are different in gain, the signal delay time tends to be deviated. As a result, the group delay error of the filter tends to be great.
SUMMARY OF THE INVENTION
An object of the present invention is providing a variable gain amplifier capable of reducing the circuit area.
Another object of the present invention is providing a filter circuit capable of reducing the group delay error.
According to one aspect of the present invention, the variable gain amplifier includes an input node pair, a first output node pair, a voltage-current converter, a plurality of first resistances, a first current source, a second current source, a second output node pair, a third output node pair and a switch circuit.
The input node pair receives a differential signal. The voltage-current converter outputs a differential current corresponding to a voltage between one and the other of the input node pair to the first output node pair. The plurality of first resistances are connected in series between one and the other of the first output node pair. The first current source is connected between a power supply node receiving the supply voltage and one of the first output node pair. The second current source is connected between the power supply node and the other of the first output node pair. The second output node pair receives a voltage at the first output node pair. The switch circuit connects an interconnection node among interconnection nodes connecting the plurality of first resistances to one of the third output node pair, and connects another interconnection node among the interconnection nodes connecting the plurality of first resistances to the other of the third output node pair.
In the variable gain amplifier described above, a differential signal supplied to the input node pair is amplified with a predetermined gain (first gain), and the amplified signal is output from the second output node pair. The differential signal is also amplified with a gain (second gain) corresponding to the resistance value between one interconnection node and another interconnection node, among the interconnection nodes connecting the plurality of first resistances, connected to the third output node pair via the switch circuit, and the amplified signal is output from the third output node pair. The second gain can be changed by changing the interconnection nodes connected to the third output node pair via the switch circuit. Thus, the variable gain amplifier described above has two functions as an amplifier having the first gain and as an amplifier having the second (variable) gain. Therefore, the circuit area can be reduced compared with the case of providing a first-gain amplifier and a second-gain amplifier separately, and thus the power consumption can be reduced.
The voltage at the second output node pair is a voltage at both ends of the plurality of first resistances, and the voltage at the third output node pair is a voltage at in-between positions of the plurality of first resistances. Therefore, the voltage at the second output node pair and the voltage at the third output node pair match in phase with each other. This reduces the difference between the signal delay in the path from the input node pair to the second output node pair and the signal delay in the path from the input node pair to the third output node pair, compared with the case of providing a first-gain amplifier and a second-gain amplifier separately.
Preferably, the voltage-current converter includes a first transistor, a second transistor, a third current source, a fourth current source and a second resistance.
The first transistor is connected between one of the first output node pair and a ground node receiving the ground voltage, and receives a voltage input via one of the input node pair at a gate function terminal. The second transistor is connected between the other of the first output node pair and the ground node, and receives a voltage input via the other of the input node pair at a gate function terminal. The third current source is connected in series with the first transistor between the one of the first output node pair and the ground node, and supplies a bias current to the first transistor. The fourth current source is connected in series with the second transistor between the other of the first output node pair and the ground node, and supplies a bias current to the second transistor. The second resistance is connected between a source function terminal of the first transistor and a source function terminal of the second transistor.
The gate function terminal corresponds to the gate when the first and second transistors are MOS transistors, and corresponds to the base when they are bipolar transistors. The drain function terminal corresponds to the drain when the first and second transistors are MOS transistors, and corresponds to the collector when they are bipolar transistors. The source function terminal corresponds to the source when the first and second transistors are MOS transistors, and correspo
Fujiyama Hirokuni
Morie Takashi
McDermott & Will & Emery
Van Nguyen Khanh
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