Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-10-22
2004-09-07
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
Reexamination Certificate
active
06788144
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a variable-gain amplifier in which the gain is changed in accordance with the input signal.
BACKGROUND OF THE INVENTION
FIG. 5
is a schematic circuit diagram illustrating an example of a conventional variable-gain amplifier.
In
FIG. 5
, Q
1
-Q
6
represent npn transistors; R
1
-R
3
represent resistors; SC
1
and SC
2
represent constant current sinks; T
1
-T
3
and T
1
′-T
3
′ represent terminals.
The base of npn transistor Q
1
is connected to terminal T
1
, and its emitter is connected to reference potential GND via constant current sink SC
1
.
The base of npn transistor Q
2
is connected to terminal T
1
′, and its emitter is connected to reference potential GND via constant current sink SC
2
.
Resistor R
3
is connected between the emitters of npn transistor Q
1
and npn transistor Q
2
.
The emitters of npn transistor Q
3
and npn transistor Q
4
are connected together and to the collector of npn transistor Q
1
. Also, the base of npn transistor Q
3
and the base of npn transistor Q
4
are connected to terminals T
2
and T
2
′, respectively.
The emitters of npn transistor Q
5
and npn transistor Q
6
are connected together and to the collector of npn transistor Q
2
. Also, the base of npn terminal Q
5
and the base of npn transistor Q
6
are connected to terminals T
2
′ and T
2
, respectively.
The collector of npn transistor Q
3
is connected to power supply Vcc via resistor R
1
and to terminal T
3
.
The collector of npn transistor Q
6
is connected to power supply Vcc via resistor R
2
and to terminal T
3
′.
The collectors of npn transistor Q
4
and npn transistor Q
5
are directly connected to power supply Vcc.
When the variable-gain amplifier shown in
FIG. 5
with the configuration is used, the differential voltage v
1
input between terminals T
1
and T
1
′ is amplified by the gain G
1
and output as differential voltage v
3
that appears between terminals T
3
and T
3
′. The gain G
1
can vary corresponding to the differential voltage v
2
input between terminals T
2
and T
2
′.
First, the relationship between gain G
1
and differential voltage v
2
will be explained.
When the differential amplifier comprised of the transistor pair of npn transistor Q
3
and npn transistor Q
4
operates outside the saturation region, current I
1
flowing through resistor R
1
can be approximated by the following equation.
I1
=
I3
/
{
1
+
exp
(
-
v2
/
V
T
)
}
=
I3
×
A
(
v2
)
&AutoLeftMatch;
(
1
)
where
VT=kT/q
(2)
A
(
v
2
)=1/{1+exp (−
v
2
/
VT
)} (3)
VT in Equation (1) represents the thermal voltage of the transistor. It is expressed as shown in Equation (2) using Boltzmann's constant k, the junction temperature T of the transistor, and the charge q on the electron.
Current I
2
flowing through resistor R
2
can be approximated using the following equation similar to Equation (1).
I
2
=
I
3
′×
A
(
v
2
) (4)
Also, when equal currents Isc flow in constant current sinks SC
1
and SC
2
, the collector current I
3
of npn transistor Q
1
and the collector current I
3
′ of npn transistor Q
2
can be approximated using the following equations.
I
3
=
Isc+Ie
(5)
I
3
′=
Isc−Ie
(6)
where Ie represents the current flowing through resistor R
3
.
Also, differential voltage v
1
is expressed as follows using the base-emitter voltage Vbe
1
of npn transistor Q
1
, base-emitter voltage Vbe
2
of npn transistor Q
2
, and resistance r
3
of resistor R
3
.
V
1
=
Vbe
1
r
3
×
Ie−Vbe
2
(7)
When resistors R
1
and R
2
have the same resistance r
1
, the differential voltage v
3
is expressed as follows.
V
3
=(
I
2
−
I
1
)×
r
1
(8)
In this case, differential voltage v
1
varies by as much as &Dgr;v
1
. If the voltage change of base-emitter voltage Vbe
1
and base-emitter voltage Vbe
2
is small compared with voltage &Dgr;v
1
, voltage &Dgr;v
1
can be expressed as follows.
&Dgr;
v
1
=
r
3
×&Dgr;
Ie
(9)
&Dgr;Ie represents the change in current Ie corresponding to the change in voltage &Dgr;v
1
.
Also, the change &Dgr;I
3
in current I
3
and the change &Dgr;I
3
′ in current I
3
′ are expressed by the following equations.
Δ
I3
=
Δ
I
e
=
Δ
v1
/
r3
&AutoLeftMatch;
(
10
)
Δ
I3
′
=
Δ
I
e
=
-
Δ
v1
/
r3
(
11
)
Based on Equations (10) and (11), the change &Dgr;I
1
in current I
1
and the change &Dgr;I
2
in current I
2
can be expressed as follows.
Δ
I1
=
Δ
I3
×
A
(
v2
)
=
Δ
v1
×
A
(
v2
)
/
r3
&AutoLeftMatch;
(
12
)
Δ
I2
=
Δ
I3
′
×
A
(
v2
)
=
-
Δ
v1
×
A
(
v2
)
/
r3
&AutoLeftMatch;
(
13
)
Based on Equations (8), (12), and (13), the change &Dgr;v
3
of differential voltage v
3
can be expressed as follows.
Δ
v3
=
(
Δ
I2
-
Δ
I1
)
×
r1
=
-
2
Δ
v1
×
A
(
v2
)
×
r1
/
r3
=
G1
×
Δ
v1
&AutoLeftMatch;
(
14
)
where
G
1
=−2
A
(
v
2
)×
r
1
/
r
3
(15)
Consequently, as shown in Equation 15, the gain G
1
of variable-gain amplifier
10
shown in
FIG. 5
can be changed corresponding to differential voltage v
2
.
The voltage drop Vt
3
at terminal T
3
with respect to power supply Vcc and the voltage drop Vt
3
′ at terminal T
3
′ with respect to power supply Vcc are expressed as followed on the basis of the equation.
Vt3
=
r1
×
I1
=
I
s
c
×
r1
×
A
(
v2
)
+
I
e
×
r1
×
A
(
v2
)
&AutoLeftMatch;
(
16
)
Vt3
′
=
r1
×
I2
=
I
s
c
×
r1
×
A
(
v2
)
-
I
e
×
r1
×
A
(
v2
)
(
17
)
In Equations (16) and (17), the second term represents a signal component that includes current Ie, which varies corresponding to the change in differential voltage v
1
, and the first term represents a certain in-phase component independent of the change in differential voltage v
1
. Also, the in-phase component varies corresponding to differential voltage v
2
. Consequently, when differential voltage v
2
is changed in order to change the gain of the variable-gain amplifier, the in-phase voltage of the output also changes correspondingly. Since there is a limit on the range of the allowable in-phase voltage in the next stage of circuit that receives differential voltage v
3
, it is necessary to limit the dynamic range of differential voltage v
3
or gain G
1
to keep the in-phase voltage within that range.
The circuit shown in
FIG. 6
is used to solve this problem of variable-gain amplifier
10
shown in FIG.
5
.
The same symbols in
FIGS. 5 and 6
represent the same respective elements. Also, in
FIG. 6
, Q
7
-Q
10
represent npn transistors, and SC
3
represents a constant current sink.
The emitters of npn transistors Q
7
-Q
10
are connected to each other and to reference potential GND via constant current sink SC
3
.
Also, the bases of npn transistor Q
7
and npn transistor Q
8
are connected to terminal T
2
, and the collectors are connected to power supply Vcc.
The base of npn transistor Q
9
is connected to terminal T
2
′, and the collector is connected to the collector of npn transistor Q
3
.
The base of npn transistor Q
10
is connected to terminal T
2
′, and the collector is connected to the collector of npn transistor Q
6
.
In the variable-gain amplifier
11
shown in
FIG. 6
, when the same current Isc as that flow
Brady III W. James
Kempler William B.
Mottola Steven J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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