Variable gain amplifier

Details Variable gain amplifier Variable gain amplifier

2002-05-03

2004-05-18

Nguyen, Khanh Van (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S260000

Reexamination Certificate

active

06737920

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a variable gain amplifier, and more specifically a variable gain amplifier with improved linearity characteristics.
BACKGROUND OF THE RELATED ART
Variable gain amplifiers (VGAs) are well known. In the communication industry, particularly for wireless communications, variable gain amplifiers are well known as being used to provide amplification of either intermediate frequency (IF) or radio frequency (RF) signals. In a variable gain amplifier, a control unit will provide a gain signal to the variable gain amplifier, and, based upon the gain signal, the variable gain amplifier will accordingly amplify an input signal by an amount corresponding to the gain signal, to obtain an amplifier output signal.
While the proper selection of the gain signal that is input to the variable gain amplifier is needed in any variable gain amplifier, the components that are used to implement the variable gain amplifier are also significant. As illustrated in
FIG. 1
, it would be desirable to obtain a variable gain amplifier in which the input signal and the output signal are linearly related, as illustrated by the plot labeled “Ideal.” While in practice this ideal is not possible, obtaining input-output characteristics that are closer to ideal is desired.
A conventional variable gain amplifier will have input-output characteristics that that are illustrated in the plot labeled “Conventional” in FIG.
1
. As seen, the greater the gain, typically the greater the amount of non-linearity that is introduced.
The most generic variable gain amplifier is a differential pair with a tail current source. The gain is adjusted by varying the bias current of the tail current source. This is continuous analog adjustment. A variant of this generic variable gain amplifier is to use a plurality of differential pairs that are digitally switched for gain control.
An exemplary conventional variable gain amplifier is illustrated in
FIGS. 2A and 2B
. As shown, the variable gain amplifier
200
contains a plurality of parallel connected gain stages
210
, with each gain stage having a common input
212
, and a common output
214
with inductive load
216
at the common output
214
. Each gain stage
210
contains a combination of an amplifier
220
and a switch
222
(further illustrated as switches M
3
and M
4
in FIG.
2
A). The amplifier
220
within each gain stage
210
will provide a portion of the gain, with the collective gain being determined by the gain from the amplifier
220
within each gain stage
210
as well as the state of the switches
222
, which determines whether the gain stage
210
is connected to the common output
212
. By powering on a different number of gain cells, current flowing into output inductors
216
is changed and results in a different gain. For example, VGA has its minimum gain by only powering on gain stage
1
. With gain stage
1
and gain stage
2
powered on, the variable gain amplifier
200
will obtain 6 dB more gain, and with all the gain stages powered on, the variable gain amplifier
200
will achieve its maximum gain.
The gain stage
210
illustrated in
FIG. 2A
is illustrated in more detail in FIG.
2
B. As shown, a differential common-source cascode amplifier is used to minimize the input impedance variation through different gain settings.
In order to maintain the accuracy of gain over a wide frequency range, such as from a 5.15 GHz lower band to a 5.825 GHz upper band of unlicensed national information structure (U-NII) bands, the input impedance of the variable gain amplifier
200
has to maintain the same value over different gain settings. Theoretically, due to Miller Effect, any capacitance across input and output nodes will be amplified by the gain and shown at the input node. As shown in
FIG. 2B
, the overlap capacitance, Cgd, of input transistors, M
1
and M
2
, will have different effective loading for input nodes, node-A and node-B, with the gain cell powered on or off. In order to reduce the variation of this effective loading over different gain settings, the cascode devices, M
3
and M
4
, are added to reduce the gain across node-A and node-G (node-B and node-H). This cascode scheme is also known as unilaterization.
While, the cascode device can reduce the gain across Cgd and minimize Miller Effect, extra transistors M
3
and M
4
are needed on the signal path. Thus, the variable gain amplifier
200
requires more voltage headroom between node-C and node-E (node-D and node-F) for the proper biasing condition. This results the drop of maximum allowable output voltage swing to (Vdd−2* Vdsat), and makes poor linearity performance for large signals. Further, the common-source is directly connected to a current source, Ibias, which is not an ideal high-impedance node. This results in poor common-mode rejection.
Amplifiers are also known which operate in a manner that decouple the inputs and outputs of the amplifier. One particular class of such amplifiers operates in a manner in which undesired feedback is cancelled. Such amplifiers are known as using a neutralization approach, rather than amplifiers that use a unilaterization approach in which signals can flow only one way over large bandwidths and thereby eliminate, rather than cancel, undesired feedback.
FIG. 3
illustrates an example of such an amplifier that uses a neutralization approach. Such amplifiers that implement a neutralization approach are not widely used. One reason for not widely being used, as discussed in “The Design of CMOS Radio Integrated Circuits” by Thomas H. Lee, pp. 203-206, Cambridge University Press, 1998 is that providing a circuit with neutralization can be difficult, since obtaining canceling can require circuits in which a capacitance must match another capacitance in order for the cancellation to occur. In many cases, however, the capacitance that must match is other voltage dependent capacitance, which can make obtaining that match across the entire operating range difficult.
The conventional manner of implementing a variable gain amplifier has been to use a circuit such as illustrated in
FIGS. 2A and 2B
, and then alter the current in order to obtain the desired variable gain, which allow such voltage dependency as discussed above to exist. Accordingly, neutralization circuits have not previously been used in variable gain amplifiers, and particularly in variable gain amplifiers implemented in CMOS. Rather, conventional circuits only use an amplifier that utilizes the unilaterization approach.
SUMMARY OF THE INVENTION
An advantage of the present invention is increased linearity across the entire range of the variable gain amplifier.
Another advantage of the present invention is providing a variable gain amplifier with stable operation characteristics as different gain stages within the variable gain amplifier are turned on and off.
It is another advantage of the present invention to provide constant input impedance through different gain settings.
A further advantage of the present invention is to provide a variable gain amplifier in which each of the various gain stages therein maximize the available voltage swing.
A further advantage of the present invention is to improve common-mode rejection performance and attenuate unwanted harmonics.
The above advantages, either singly or in combination, among others, are achieved by different aspects of the present invention.
In one aspect, the present invention provides a variable gain amplifier with a plurality of gain stages in which each of the gain stages is implemented using a circuit that implements a neutralization approach.
The above and other aspects of the present invention will be described herein.


REFERENCES:
patent: 5838199 (1998-11-01), Nakamura
patent: 6084473 (2000-07-01), Nauta et al.
patent: 6392490 (2002-05-01), Gramegna et al.
patent: 6552612 (2003-04-01), Wilson
patent: 2001007667 (2001-01-01), None
patent: WO 02/03548 (2002-01-01), None
Mataya et al., “IF Amplifier Using CcCompensated Transistors,”IEEE Journal of Solid-State Circuits(1968) vol.

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