Amplifiers – With control of power supply or bias voltage – With control of input electrode or gain control electrode bias
Reexamination Certificate
2001-09-25
2003-10-07
Tokar, Michael (Department: 2819)
Amplifiers
With control of power supply or bias voltage
With control of input electrode or gain control electrode bias
C330S134000, C330S285000, C330S302000, C330S310000
Reexamination Certificate
active
06630861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to variable gain amplifiers, and more specifically, the present invention relates to a high-frequency variable gain amplifier, preferably for use in a communications device for transmitting and receiving high-frequency signals, which is capable of a low-gain operation and an attenuating operation.
2. Description of the Related Art
A receiver circuit for wireless communications involves a considerably wide range of reception levels. For this reason, a level control is required in a radio frequency band amplification unit at a location upstream of a reception mixer. Meanwhile, in a transmitter circuit, an adjustment of the transmission power level is required in order to reduce distortions on the receiving end and to control the transmission power level in accordance with the distance to the receiver. The amplification and attenuation operations in accordance with the level of an input signal and the adjustment of the transmission power level have been achieved by a variable gain amplifier primarily composed of an amplifier and a variable resistor.
FIG. 5
shows an example of such a variable gain amplifier. As shown in
FIG. 5
, in the variable gain amplifier, between an input terminal
71
to which a high-frequency signal is applied and an output terminal
72
from which a high-frequency signal is output, a common-source FET
73
is provided as an amplifier. The gate of the FET
73
is connected to the input terminal
71
via a capacitor
75
, and the drain of the FET
73
is connected to the output terminal
72
via a capacitor
76
. Furthermore, the drain of the FET
73
is connected to a drain power supply terminal
77
via an inductor
80
so that a voltage is applied from the drain power supply terminal
77
to the drain of the FET
73
. The gate of the FET
73
is connected to a gate power supply terminal
78
via a resistor
81
so that a voltage is applied from the gate power supply terminal
78
to the gate of the FET
73
.
Furthermore, between the drain and the gate of the FET
73
, a FET
74
is provided as a variable resistor which negatively feeds back output from the drain of the FET
73
to the gate of the FET
73
. The drain of the FET
74
is connected to the drain of the FET
73
, and the source of the FET
74
is connected to the gate of the FET
73
via a capacitor
83
. The capacitor
83
is provided in order to separate DC voltage between the drain and the gate of the FET
73
. Furthermore, between the source and the drain of the FET
74
, a resistor
84
is provided so that the source voltage and the gate voltage of the FET
74
will be substantially the same. Furthermore, the gate of the FET
74
is connected to a control terminal
79
via a resistor
82
so that a voltage is applied from the control terminal to the gate of the FET
74
via the resistor
82
.
When the voltage applied to the control terminal
79
is changed, the gate voltage of the FET
74
changes accordingly, and in accordance therewith, the resistance between the source and the drain of the FET
74
changes, such that the FET
74
functions as a variable resistor. When the gate voltage of the FET
74
increases, the resistance between the source and the drain of the FET
74
decreases. As a result, the amount of negative feedback from the drain of the FET
73
to the gate of the FET
73
increases, decreasing the gain of the FET
73
. On the other hand, when the gate voltage of the FET
74
decreases, the resistance between the source and the drain of the FET
74
increases. Consequently, the amount of negative feedback from the drain of the FET
73
to the gate of the FET
73
decreases, increasing the gain of the FET
73
. variable gain amplifier.
FIG. 6
shows a multistage variable gain amplifier that is implemented using the variable gain amplifier shown in FIG.
5
. In the multistage variable gain amplifier, between an input terminal
71
to which a high-frequency signal is applied and an output terminal
72
to which a high-frequency signal is output, FETs
85
and
91
are provided as amplifiers, upstream and downstream of the variable gain amplifier shown in
FIG. 5
, respectively.
More specifically, between the input terminal
71
and the output terminal
72
, a common-source FET
85
used as an amplifier, the variable gain amplifier shown in
FIG. 5
, and a common-source FET
91
used as an amplifier are provided. The gate of the FET
85
is connected to the input terminal
71
via a capacitor
86
, and the drain of the FET
85
is connected to the capacitor
75
of the variable gain amplifier shown in FIG.
5
. The gate of the FET
91
is connected to the capacitor
76
of the variable gain amplifier shown in
FIG. 5
, and the drain of the FET
91
is connected to the output terminal
72
via a capacitor
92
.
Furthermore, the drain of the FET
85
is connected to a drain power supply terminal
87
via an inductor
89
so that a voltage is applied from the drain power supply terminal
87
to the drain of the FET
85
. The gate of the FET
85
is connected to a gate power supply terminal
88
via a resistor
90
so that a voltage is applied from the gate power supply terminal
88
to the gate of the FET
85
.
Furthermore, the drain of the FET
91
is connected to a drain power supply terminal
93
via an inductor
95
so that a voltage is applied from the drain power supply terminal
93
to the drain of the FET
91
. The gate of the FET
91
is connected to a gate power supply terminal
94
via a resistor
96
so that a voltage is applied from the gate power supply terminal
94
to the gate of the FET
91
. The variable gain amplifier is thus implemented as a multistage variable gain amplifier.
In the variable gain amplifiers shown in
FIGS. 5 and 6
, in order to provide the FET
74
used as a variable resistor between the drain and the gate of the FET
73
used as an amplifier, the capacitor
83
is connected in series with the FET
74
, separating DC voltage between the drain and the gate of the FET
73
.
However, the capacitor
83
has a high impedance in lower frequencies if the capacitance thereof is small, causing limitations on gain control with respect to lower frequencies. Thus, when the variable gain amplifier is implemented in a microwave monolithic integrated circuit (hereinafter abbreviated as MMIC), the capacitor
83
occupies a significantly large area, thereby increasing the size of the MMIC. Furthermore, depending on the capacitance of the capacitor
83
, the phase of the feedback is reversed from negative to positive around the cutoff frequency of the capacitor
83
, destabilizing the circuit and causing an oscillation.
Furthermore, when the variable gain amplifier is implemented in an MMIC, in order to test whether the FETs in the MMIC have been properly arranged, the drain, the source, and the gate of each of the FETs must be connected to a tester for DC voltage. Thus, if the source of the FET
74
used as a variable resistor is separated from external terminals (gate power supply terminal, drain power supply terminal, etc.) for DC voltage by the capacitor
83
, a testing terminal must be provided and connected to the source of the FET
74
, thereby further increasing the chip size of the MMIC.
SUMMARY OF THE INVENTION
In order to solve the problems described above, preferred embodiments of the present invention provide a variable gain amplifier in which oscillations around the cutoff frequency of a DC-cutoff capacitor used in a feedback circuit are prevented, and which allows for a much smaller MMIC implementation.
According to a preferred embodiment of the present invention, a variable gain amplifier includes at least two amplifiers for amplifying a signal, the at least two amplifiers being connected in series with one another, and a variable resistor having a resistance that is controlled in accordance with a voltage applied to a control terminal, the variable resistor being connected between the outputs of two of the at least two amplifiers having opposite output phase
Keating & Bennett LLP
Murata Manufacturing Co. Ltd.
Nguyen Linh V
Tokar Michael
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