Computer graphics processing and selective visual display system – Display peripheral interface input device – Including keyboard
Reexamination Certificate
1995-01-05
2003-11-18
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Including keyboard
C341S026000, C708S100000, C708S190000
Reexamination Certificate
active
06650317
ABSTRACT:
This invention relates to calculators and, more particularly, to a variable function fixed program calculator capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary semiconductor technology.
It is an object of the present invention to provide a system which functions as a basic desk top calculator. More particularly, it is an object of the invention to provide such calculator function including primitive decimal operations, such as add, subtract, multiply and divide with floating decimal point entry and either floating or fixed decimal point results on multi-digit operands. This object is accomplished in accordance with the present invention by providing, for example, a dynamic charge storage random access memory shifting array for registration of numeric and control data. The calculator includes a control memory such as a programmable logic array (PLA), a program memory such as a read only memory (ROM) and means for performing arithmetic and logic modification of registered data including binary coded decimal (BCD), bit-parallel digit-serial decimal arithmetic, and set-reset-toggle (SRT) FLAG data modification.
Another object of the invention is to provide a calculator system which is capable of being fabricated as a monolithic integrated semiconductor system. More particularly, it is an object of the invention to provide such calculator system which is capable of being fabricated as a monolithic integrated metal-insulator-semiconductor system utilizing contemporary metal-insulator-semiconductor technology. This object is accomplished in accordance with the present invention by providing a random access memory shift register system which requires approximately one-third the area of conventional shift register systems, providing internal generation of multi-phase clocks from a single phase input clock which is included in the calculator but which is external to the monolithic structure and by providing a common programmed scanning system in the monolithic structure to provide both keyboard encoding and display decoding with minimum external connections between the monolithic system and the keyboard and display The total number of connections from the monolithic structure to other calculator subsystems such as the keyboard, display and power supply are therefore minimized so that the monolithic structure is capable of being packaged in a conventional twenty-eight or forty pin package.
It is a further object of the present invention to provide a versatile calculator system in which the calculator function and input and output interfaces can be varied without changing the basic calculator structure, and particularly without changing the basic calculator structure as an integrated semiconductor system. This object is accomplished with the present invention by providing a programmable read only memory which provides a fixed program for the calculator system in accordance with the desired function of the calculator system and by providing programmable logic arrays for decoding and encoding the input, output and operating data by masking such data to any desired format. The programmable read only memory and the programmable logic arrays are easily modified by changing only the gate-insulator mask for the metal-insulator-semiconductor integrated system embodiment during the fabrication process.
Yet another object of the invention to provide a calculator with improved means for encoding keyboard commands and status information and which also functions as a direct interface means between a display decoder and a display for segmented and/or individual-decimal-numerical displays. This object is accomplished in accordance with the invention by providing a programmed scanning system to service both the keyboard input and display output, thereby minimizing hardware requirements for the key input system. Four keyboard input pins combine with eleven scanner output pins to allow a total of forty-four distinct keys and/or switches. The programmed routine residing in the read-only memory encodes the input from the keyboard array under program control. The scanning system operates at a slow enough rate to eliminate the need for any external keyboard drive circuitry and allows direct drive of large capacitance loads with response consistent to the scan rate. The scan program includes an encoding routine to effectively defeat transient noise and key bounce types of interference from the keyboard. An additional advantage of the keyboard scanning system then is that it requires few diodes, no amplifiers and simple switches which need not be low resistance or low bounce time switches. The display output includes internal segment or digit decoding, digit-blanking and zero suppression logic and utilizes the same scanning system as the keyboard. The display itself may be comprised of light-emitting diodes, liquid crystal, cold cathode gas discharge display elements, fluorescent display elements, multi-digit single-envelope cold-cathode gas-discharge tubes, incandescent display elements, etc. The multiple display capability is provided by the generally defined digit scanning and segment or numeral decoding system and by providing for an inter-digit blanking signal which is variable in terms of leading and trailing edge blanking intervals and in terms of its application to either the segment drivers or the digit drivers or both. The output decoder is comprised of a programmable logic array segment decoder circuit which can be programmed to accommodate any seven, eight, nine, ten segment or ten digit numerical display font plus a right or left decimal point. In this manner the calculator system of the present invention is essentially insensitive to the selection of a display which is utilized in conjunction with it.
It is still a further object of the invention to provide internal means for suppression of insignificant leading zeros in the calculator display. This object is accomplished by the programmed scanning system which provides scanning of the most significant output digits first and minimizes hardware means for detecting and suppressing leading zeros.
Another object of the invention is to allow both constant-operand and chained-intermediate-result type of calculations in a fully algebraic manner. This object is accomplished by providing an operator selectable control or mode switch to distinguish the constant-operand mode from the chained-intermediate-result mode of operation and by providing a fixed program decision routine in the read only memory array to detect the desired mode and effect it.
It is yet a further object of the invention to provide a calculator system which includes means for providing an automatic round-off solution for high accuracy in calculation. This object is accomplished in accordance with the present invention by utilizing a fixed program routine stored in the read only memory which adds the numeral five to the least significant digit which is to be lost. In this manner, a one is added to the second least significant digit which is to be kept when the least significant digit which is to be lost is greater than or equal to five.
Another object of the invention is to provide a calculator system with minimum power dissipation in order to provide a uniquely portable desk top calculator with good battery life. This object is accomplished in accordance with the present invention by provision of special control circuits to turn off dissipating functional elements except when such functional elements are actually being used and by provision of special pre-charge ratioless circuits within an metal-insulator-semiconductor embodiment of the read only memory, programmable logic array and arithmetic logic unit functional subsystems. For example, the instruction output from the read only memory need be detected only one per instruction cycle; a power control is applied to the read only memory decoder effecting a duty cycle of {fraction (2/13)}ths of the nominal static power dissipation to eliminate DC currents so that only transient CV
2
f powe
Boone Gary W
Cochran Michael J
Bassuk Lawrence J.
Brady W. James
Mengistu Amare
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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