Variable-frequency pulse generator

Details Variable-frequency pulse generator Variable-frequency pulse generator

2004-03-02

2004-11-23

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S113000

Reexamination Certificate

active

06822492

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a variable-frequency pulse generator capable of generating a pulse of the desired frequency.
BACKGROUND ART
A conventional variable-frequency pulse generator will be explained below. A conventional variable-frequency pulse generator has been disclosed in Japanese Patent Application No. 11-220364.
FIG. 12
shows a configuration of a variable-frequency pulse generator disclosed in the above publication.
In
FIG. 12
, the reference symbol
100
denotes a conventional variable-frequency pulse generation circuit,
101
denotes a bit inverter which inverts a first reference value D
1
,
102
denotes a data selector which selects either one of the output of the inverter
101
and a pulse number set value Ps,
103
denotes a digital adder which adds the output &thgr;1 of a first data holding circuit described later and the output of the data selector
102
, and
104
denotes the first data holding circuit which latches the output &thgr;2 of the digital adder
103
at the timing T
2
of a reference clock fb. The reference symbol
105
denotes a first data comparator which compares the output &thgr;1 of the first data holding circuit
104
and the first reference value D
1
, and
106
denotes a second data comparator which compares the output &thgr;1 of the first data holding circuit
104
and a second reference value D
2
. The reference symbol
107
denotes a pulse generation circuit which judges the output level (High or Low) based on the two comparison results,
108
denotes a second data holding circuit which latches the output fd of the pulse generation circuit
107
at the timing T
3
of the reference clock fb and outputs a pulse train fout, and
109
denotes an overflow prevention circuit which outputs the overflow prevention signal fob synchronous with the reference clock fb based on the comparison result of the first data comparator
105
.
The control clock frequency fc is [fb/4]. The first reference value D
1
is [fc×n], and the second reference value D
2
is [(fc/2)×n]. The pulse number set value per n seconds Ps is [Vp×n], and the value thereof can be set for 1 unit in the range of [0≦Ps≦{(fc/2)×n}]. n denotes the maximum cycle of the output pulse, and Vp denotes a speed set value.
The operation of the conventional variable-frequency pulse generator will now be explained. The inverter
101
outputs a bit inversion value of the reference value D
1
in the 26-bit notation. When the S terminal is 0 (&thgr;1≦D
1
), the data selector
102
outputs the pulse number set value Ps (26-bit notation) of a terminal A to a terminal Y, and when the S terminal is 1 (&thgr;1>D
1
), the data selector
102
outputs the bit inversion value of the reference value D
1
of a terminal B to the terminal Y.
When a CIN terminal is 0 (&thgr;1≦D
1
), the digital adder
103
adds the pulse number set value Ps output from the data selector
102
and the output &thgr;1 of the first data holding circuit
104
, and when the CIN terminal is 1 (&thgr;1>D
1
), the digital adder
103
adds −(fc×n), being the sum of the output of the data selector
102
and CIN=1, and the output &thgr;1 of the first data holding circuit
104
, and outputs the addition result &thgr;2 (26-bit notation) for each case. The first data holding circuit
104
latches the addition result &thgr;2 at the timing T
2
of the reference clock fb and the overflow prevention signal fob, and outputs data &thgr;1 (26-bit notation).
The first data comparator
105
compares the output &thgr;1 of the first data holding circuit
104
and the first reference value D
1
, and when &thgr;1>D
1
, outputs 1 as the overflow signal. The second data comparator
106
compares the output &thgr;1 of the first data holding circuit
104
and the second reference value D
2
. The pulse generation circuit
107
judges the both comparison results, and for example, when the comparison results by the both comparators are 0≦&thgr;2<D
2
(=(fc/2)×n), outputs 0 as the judgment result fd, and when D
2
≦&thgr;2<D
1
(=fc×n), outputs 1, and when D
1
≦&thgr;2, outputs 0. The second data holding circuit
108
latches the judgment result fd at the timing T
3
of the reference clock fb, and outputs a pulse train fout.
The overflow prevention circuit
109
receives the overflow signal output from the first data comparator
105
at the timing T
4
of the reference clock fb, and outputs an overflow prevention signal fob.
FIG. 13
is a timing chart which shows the operation of the conventional variable-frequency pulse generator. At first, the speed change timing &Dgr;t changes at a period synchronous with the timing T
1
of the reference clock fb and the speed change timing, and acceleration and deceleration speed is latched at the timing T
1
of the reference clock fb. This operation is executed by the part other than the configuration shown in FIG.
12
.
The first data holding circuit
104
latches the output &thgr;2 of the digital adder
103
at the timing T
2
of the reference clock fb. The second data holding circuit
108
then latches the output fd of the pulse generation circuit
107
at the timing T
3
of the reference clock fb, and outputs the pulse train fout.
The overflow prevention circuit
109
performs overflow prevention processing with respect to the output &thgr;1 of the first data holding circuit
104
, at the timing T
4
of the reference clock fb. That is, when overflow occurs (&thgr;1>D
1
), and fb=(High), the overflow prevention circuit
109
outputs the overflow prevention signal fob (=High).
However, in the conventional variable-frequency pulse generator, control for four cycles of the reference clock is necessary during the period of from the speed setting until the overflow prevention processing is completed, that is, during 1 cycle of output control of the pulse train fout. Therefore, the reference clock of a frequency of 8 times or more is required in order to actually obtain the pulse train of a desired frequency (see FIG.
13
). As a result, in the conventional variable-frequency pulse generator, with the speed-up of the reference clock, there is caused a problem in that the noise, power consumption and heat generation of the whole apparatus considerably increase.
It is an object of the present invention to provide a variable-frequency pulse generator capable of reducing the noise, power consumption and heat generation compared to the conventional apparatus.
DISCLOSURE OF THE INVENTION
The variable-frequency pulse generator according to the present invention has a configuration such that one cycle of output control of the pulse train is executed by two cycles of the reference clock, and for example, comprises an inversion unit (corresponding to an inverter
11
in the embodiment described later) which inverts a first reference value regulated by the reference clock, a selection unit (corresponding to a data selector
12
) which selects the first reference value after inversion, when an overflow has occurred, and in any other event selects a predetermined value which changes depending on a set speed, a data holding unit (corresponding to a first data holding circuit
14
) which latches an output of a previous stage, being the present value of a result of addition, in the second cycle of the reference clock and at a predetermined timing of an overflow prevention signal, an addition unit (corresponding to a digital adder
13
) which adds the value selected by the selection unit and the data latched by the data holding unit, a first comparison unit (corresponding to a first data comparator
15
) which compares the value obtained by the addition unit as a result of addition and the first reference value, a second comparison unit (corresponding to a second data comparator
16
) which compares the value obtained by the addition unit as a result of addition and a second reference value which is half of the first reference value, a judg

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