Variable frequency oscillator, and phase locked loop and...

Details Variable frequency oscillator, and phase locked loop and... Variable frequency oscillator, and phase locked loop and...

2001-01-05

2003-03-18

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S034000, C331S17700V, C327S270000, C327S274000

Reexamination Certificate

active

06535070

ABSTRACT:

The present invention relates to a phase locked loop (hereinafter, referred to as “PLL”) using a variable frequency oscillator, particularly to a variable frequency oscillator preferably applied to a semiconductor integrated circuit device operated at low power supply voltage.
A large-scaled semiconductor integrated circuit device (hereinafter, referred to as “LSI”) integrated with a microprocessor has been developed intensively and large scale formation, high speed formation and low power consumption have been achieved and are being improved. A microprocessor is an operation device for executing operations as instructed by a program or the like and is operated in synchronism with clocks. A frequency synthesizer using a PLL is well known as a circuit for generating clocks (refer to, for example, D. Mijuskovic et al. “Cell Based Fully Integrated CMOS Frequency Synthesizer”, IEEE Journal of Solid-State Circuits, Vol. SC-29 (issued in March, 1994), p.271-p.279).
FIG. 11
shows a constitution of a frequency synthesizer generally used in LSI.
In
FIG. 11
, a feedback loop is formed by a phase detector
1
, a loop filter
3
and a current controlled oscillator
7
. The current controlled oscillator
7
(hereinafter, abbreviated as “ICO”) outputs a clock signal fvco in synchronism with a reference signal fr from outside. ICO
7
is a variable frequency oscillator for changing an oscillation frequency in accordance with an input current. Further, a divider
9
is a divider for generating the reference signal for dividing an input signal fi at a low frequency inputted from a quartz oscillator or the like from the outside. A divider
8
is a divider for feedback inserted into the feedback loop and by pertinently setting respective numbers of divisions of both, the clock signal fvco at a predetermined frequency can be provided. Further, a comparison signal fp to the phase detector
1
is outputted from the divider
8
.
In this case, the basic function of the constitution shown by
FIG. 11
resides in PLL for forming a signal the phase of which is synchronized with that of the input signal by the feedback loop. Installation of the dividers
8
and
9
is arbitrary and PLL functions particularly as a frequency synthesizer by installing these. Further, PLL constitutes a clock generating circuit when an output signal is a clock signal.
When such a frequency synthesizer is formed by LSI, there is adopted a constitution in consideration of special properties of a semiconductor integrated circuit. That is, in a semiconductor integrated circuit, there is a case in which although a capacitor is easy to provide, a resistor is difficult to form and formation of inductance is very difficult. Hence, the loop filter
3
is formed by a capacitor, charge and discharge of a current to and from the capacitor is carried out by a charge pump
2
and the loop filter
3
is bypassed by installing an auxiliary charge pump (hereinafter, abbreviated as “ACP”)
5
. ACP
5
executes an operation equivalent to that of a resistor and forms a zero point in a transfer function of the feedback loop. By providing the zero point, the feedback loop is stabilized.
The phase detector
1
detects a phase difference between the reference signal fr and the output signal fp of the divider
8
and outputs UP signal (a control signal for increasing a frequency) and DN signal (a signal decreasing a frequency) for controlling ICO
7
. Further, at the same time, ICO
7
outputs UPB signal and DNB signal which respectively constitute inverted signals of UP signal and DN signal. The UP signal and DN signal are pulse width modulation signals in correspondence with the phase difference between the reference signal fr and the comparison signal fp.
Further, when ICO
7
is constituted of a semiconductor integrated circuit, there is a tendency in which improvement of linearity of a relationship between an oscillation frequency and a current is more facilitated than that of a relationship between an oscillation frequency and a voltage and accordingly, ICO
7
is adopted more preferably than a voltage controlled oscillator (VCO) and a voltage-to-current converter (hereinafter, abbreviated as “VIC”)
4
converts a voltage across terminals of a capacitor of the loop filter
3
into a current. Further, ACP
5
is constituted to output a current and accordingly, the output currents from the VIC
4
and ACP
5
are added at an adder
6
for forming the above-described bypass.
Next, an explanation will be given of principal circuits of such PLL.
FIG. 12
shows constitutions of the charge pump
2
and the loop filter
3
. The charge pump
2
is constituted of switches
12
and
13
comprising 2 sets of transistors and current sources
10
and
11
and inputs UP signal and DNB signal from the phase detector
1
. In this case, UP signal and DN signal are effective when they are 0. Further, the loop filter
3
is connected to an output of the charge pump
2
and is constituted of a capacitor Cp.
The charge pump
2
charges and discharges electric charge in correspondence with inputted UP signal and inputted DNB signal from electric charge stored in the capacitor Cp of the loop filter
3
. In this case, amounts of electric charge which are charged and discharged become values derived from current values Iup and Idn of the current sources
10
and
11
constituting the charge pump
2
multiplied by a difference between a pulse width of UP signal and a pulse width of DNB signal.
FIG. 13
shows an example of VIC
4
for converting a voltage across terminals of a capacitor into a current (refer to, for example, Ilya Novof “Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter”, IEEE ISSCC '95 Digest Technical Papers (issued in February, 1995) p.112-p.113).
Such VIC is provided with a circuit constitution in which 3 stages or more of transistors each operating in a saturation region are cascaded and 3 V or more of power supply voltage is needed.
Successively, owing to special properties of a semiconductor integrated circuit mentioned above and a request for high speed operation, ICO
7
is normally constituted of a ring oscillator which plural delay cells of a current control type having gain are cascaded and the output of the final stage delay cell is fed back to the input of the first delay cell (refer to, for example, B. Razavi “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits”, p.1-p.39, issued by IEEE Press, 1996).
FIG. 14
shows an example of a delay cell. Transistors M
21
and M
22
for inputting differential signals Vin signal polarities of which are inverted each other and outputting divided signals Vout constitute a differential amplifier and transistors M
23
and M
24
constitute load resistances of these. Transistors M
25
and M
26
connected to respective output terminals of the differential amplifier constitute a positive feedback circuit and negative resistance formed by the positive feedback cancels the above-described load resistances. Thereby, the load resistances are increased apparently. Further, each of the transistors M
25
and M
26
is an amplifier having a gate electrode as an input terminal and a drain electrode as an output terminal and the positive feedback circuit is constituted of connecting the input and output terminals to intersect with each other.
Transistors M
27
and M
28
for inputting a frequency control signal Vcont respectively change a common source current of the transistors M
23
and M
24
and a common source current of the transistors M
25
and M
26
and change the apparent load resistances mentioned above. Although not illustrated, the output terminal of the amplifier is provided with parasitic capacitance and a time constant is formed by the parasitic capacitance and the apparent load resistance, and the time constant is changed by changing the apparent load resistance. That is, a delay amount of the delay cell is changed by current to thereby change the oscillation frequency of ICO
7
which is a ring oscillator in which the plural delay cell

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