Variable frequency-dividing circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3072727, 377121, H03L 700

Patent

active

051480506

ABSTRACT:
One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of the D flip-flop circuit FF1. One output signal of the D flip-flop circuit FF1 is supplied to an edge-trigger type flip-flop circuit FF4. A NAND circuit NA generates a reset signal in accordance with the output signal of the edge-trigger type flip-flop circuit FF4 and a frequency-dividing switching control signal which changes the frequency-dividing ratio, and sends the reset signal to the D flip-flop circuit FF3. These D flip-flop circuits FF1, FF2, FF3 and FF4 frequency-divide a clock signal by an odd number or an even number. The D flip-flop circuits FF1, FF2, FF3 and FF4 each comprise multiple NOR gates, which each include field-effect transistors. The current-driving performance of the field-effect transistors constituting the NOR gates to which feedback circuits, such as the wirings W1 and W2, are connected as a load, is set almost two to four times that of the field-effect transistors constituting those NOR gates where no feedback circuits are connected.

REFERENCES:
patent: 4103184 (1978-07-01), Suzukie et al.
patent: 4637039 (1987-01-01), Huizer
patent: 4733110 (1988-03-01), Hara
patent: 4902909 (1990-02-01), Chantepie

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