Variable field partial write data merge

Details Variable field partial write data merge Variable field partial write data merge

1981-01-05

1985-05-28

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900, G06F 912

Patent

active

045204390

ABSTRACT:
A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A starting bit code defines the location of the start of the bit field to be written and a field length code defines the number of bits that are to be merged and written. The combination of the starting bit code and the field length code define the ending bit control for the bits to be written, and are further utilized to control word boundary crossing into the next sequentially addressed memory word when the bit field to be written cannot be completed in the addressed word. Mask signals are generated for all bit positions that precede the starting bit code and that follow the ending bit code so that bit positions of data words read from memory that correspond to the mask bits are merged unaltered with the variable field bits that are to be written and the merged data words are thereafter returned for storage in the memory system. Bit mask signals are generated for all like-ordered bits in each byte and byte mask signals are generated to enable setting of mask configurations for all bytes in which at least one bit is to remain unaltered, through the use of decode and translator circuits coupled to control bit mask circuits and byte mask circuits.

REFERENCES:
patent: 3781812 (1973-12-01), Wymore et al.
patent: 4103329 (1978-07-01), Davis et al.
patent: 4109310 (1978-08-01), England et al.

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