Oscillators – Relaxation oscillators
Reexamination Certificate
2000-05-10
2002-06-04
Grimm, Siegfried H. (Department: 2817)
Oscillators
Relaxation oscillators
C332S109000, C323S288000, C363S041000
Reexamination Certificate
active
06400232
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to circuitry for controlling power supplies, and more specifically to oscillator circuitry for generating variable duty cycle PWM signals from which power supply operation can be controlled.
BACKGROUND OF THE INVENTION
As the number and complexity of electronic systems for automotive applications has grown in recent years, so too have power dissipation requirements for such systems. In an attempt to manage and conserve electrical power in the automotive environment, designers of automotive electronic systems have developed switchable power supplies that may themselves be electronically controlled to thereby reduce power dissipation in electrical components connected to such supplies. One particular class of switchable power supplies utilizes a pulse-width modulated (hereinafter “PWM”) signal with a variable duty cycle to control the power supply in such a manner as to down regulate battery voltage to certain electrical components under certain operating conditions. An example of one known switchable power supply utilizes a boost supply and a PWM signal with a variable duty cycle to control the switching operation of a power transistor to thereby pulse-width modulate the battery voltage supplied to certain electrical components. In this design, an error amplifier with feedback monitors the boost voltage and compares it to the battery voltage. The output of this error amplifier is compared to an oscillating ramp signal of an oscillation circuit, and the result of this comparison is a PWM signal that is used to control the operation of the power transistor. The comparator thresholds, along with the charge and discharge rates of the ramp signal, control the minimum and maximum duty cycles of the PWM signal.
One example of a known oscillator circuit
10
for generating an oscillating ramp signal, comparing the ramp signal to an error signal provided by an error amplifier, and generating a PWM signal therefrom as just described, is shown in FIG.
1
. Referring to
FIG. 1
, oscillator circuit
10
includes a series-connected resistor ladder comprising resistors R
1
,R
2
, R
3
and R
4
, wherein one end of R
1
is connected to a supply voltage VCC and one end of R
4
is connected to ground potential. The common connection of R
1
and R
2
defines a first reference voltage VR
1
and is connected to an inverting input of a first comparator C
1
. The common connection of R
2
and R
3
likewise defines a second reference voltage VR
2
and is connected to an inverting input of a second comparator C
2
, while the common connection of R
3
and R
4
defines a third reference voltage VR
3
and is connected to an inverting input of a third comparator C
3
. A fourth comparator C
4
is also provided and includes an inverting input receiving an error signal ERR from output of an error amplifier (not shown) comparing the boost voltage to the battery voltage. A resistor ROSC is connected at one end to VCC and at an opposite end to one end of a capacitor C having an opposite end connected to ground potential. The common connection of ROSC and C defines an oscillating ramp signal OSC and is connected to the non-inverting inputs of comparators C
1
-C
4
as well as to a collector of a NPN transistor Q
4
.
The output of comparator C
3
defines a comparator voltage VC
3
and is fed through an inverter to a “set” input S of a first latch circuit L
1
. A “reset” input R of latch circuit L
1
receives comparator voltage VC
1
defined by an output of comparator C
1
. Likewise, the output of comparator C
2
defines a comparator voltage VC
2
and is supplied to a “reset” input R of a second latch circuit L
2
, and the output of comparator C
4
defines a comparator voltage VC
4
and is supplied to a “set” input S of latch circuit L
2
. A “Q” output of latch circuit L
1
is connected to the base of a NPN transistor Q
1
having an emitter connected to ground potential and a collector connected to the base of a NPN transistor Q
2
, the collector of a NPN transistor Q
3
and one end of a current source Ix having an opposite end connected to VCC. The emitter of Q
2
is connected to the bases of Q
3
and Q
4
, and the emitters of Q
3
and Q
4
are connected to the bases of NPN transistors Q
8
and Q
5
as well as to the collector of Q
5
. The collector of Q
8
is connected to the collector of a NPN transistor Q
7
and defines the circuit output PWMOUT, and the base of Q
7
is connected to the “Q” output of latch circuit L
2
. The emitters of Q
5
, Q
7
and Q
8
are connected to ground potential.
Referring now to
FIG. 2
, which is composed of
FIGS. 2A-2G
, some of the signals associated with the operation of oscillator circuit
10
of
FIG. 1
are illustrated. The outputs VC
1
22
(
FIG. 2F
) and VC
3
20
(
FIG. 2E
) of comparators C
1
and C
3
respectively control the OSC waveform
24
(
FIG. 2G
) by the use of latch circuit L
1
and associated transistor circuitry. The PWM output signal
12
(
FIG. 2A
) is created by the interaction of the same transistor circuitry (Q
1
-Q
8
) and the output voltage VC
2
18
(
FIG. 2D
) of comparator C
2
. The variability in the duty cycle of the PWMOUT signal
12
is accomplished by the interaction of the output voltage VC
4
14
(FIG.
2
B), which is the comparison of the ERR signal
25
(
FIG. 2G
) and the OSC signal
24
.
The threshold voltages for the OSC signal
24
are VR
1
26
and VR
3
30
(FIG.
2
G), and the output voltage VL
1
16
(FI.
2
C) of latch circuit L
1
provides the maximum duty cycle of the PWMOUT signal
12
when ERR
25
is above the peak of the OSC signal
24
. The duty cycle of PWMOUT in this case is dependent upon the ratio of the charge and discharge times of the capacitor C. The minimum duty cycle of PWMOUT
12
occurs when ERR
25
is below the peak of the OSC signal
24
, and in this state, the PWMOUT signal
12
is the inverse of VC
2
18
which holds the latch circuit L
2
in reset, wherein the threshold voltage for the switching of VC
2
18
is VR
2
28
(FIG.
2
G). As ERR
25
increases between the lower and upper peaks of OSC
24
, the output of latch circuit L
2
is modified by the interaction of VC
4
14
which sets the latch circuit L
2
.
While the prior art circuit
10
of
FIG. 1
is operable as described to provide a variable duty cycle PWM output signal, there are several drawbacks with the structure and operation of this circuit. For example, the minimum and maximum duty cycles of the PWMOUT signal
12
may vary depending upon variations in circuit component operation; i.e., with the charging and discharging times of capacitor C as well as with the operation of comparator C
2
. In any case, the minimum and maximum duty cycles of the PWMOUT signal
12
are not fixed as would be desirable in a circuit of this type. As another example, many different circuit parameters contribute to the variation of the duty cycle of PWMOUT
12
between the minimum and maximum duty cycles thereof. Accordingly, this variation is subject to multiple sources of error, and very accurate circuit operation therefore cannot be guaranteed or expected. What is therefore needed is an improved oscillator circuit for generating an accurate variable duty cycle PWM signal with fixed minimum and maximum duty cycles. Ideally, such an improved oscillator circuit is provided in accordance with a simplified circuit design utilizing minimum circuitry and minimal signal comparisons.
SUMMARY OF THE INVENTION
The foregoing shortcomings of the prior art are addressed by the present invention. In accordance with one aspect of the present invention, an oscillator circuit comprises an oscillation circuit producing a first periodic clock signal as a function of a first capacitor, a second periodic clock signal as a function of a second capacitor and a periodic ramp signal as a function of a third capacitor, a comparator circuit responsive to an error signal and the periodic ramp signal to produce a third clock signal as a function thereof, and a logic circuit responsive to the first, second and third clock signals to produce a perio
Francisco Gregg Nelson
Good Brian K.
Gose Mark Wendell
LandOfFree
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