Variable division method and variable divider

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S115000

Reexamination Certificate

active

10545718

ABSTRACT:
A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of an inverting
oninverting unit (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the inverting
oninverting unit (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the inverting
oninverting unit (304). The fixed divider (305) divides the clock signal before division from the inverting
oninverting unit (304) according to the leading edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the leading edge of the input clock signal).

REFERENCES:
patent: 4837721 (1989-06-01), Carmichael et al.
patent: 5422584 (1995-06-01), Waters
patent: 5969548 (1999-10-01), Knapp
patent: 11-055108 (1998-02-01), None
patent: 11-150472 (1999-06-01), None
patent: 11-186900 (1999-07-01), None
“Frequency divider generates 50% duty cycle” by Andrzej Partyka;EDN—Electrical Design News; Sep. 3, 1987; No. 18; Newton, MA; pp. 244/246.
“Handbook of Logic Circuits”, J.D. Lenk, pp. 123-125, Reston Publishing Company, Inc. 1972.
“CMOS Analog Circuit Design Technique”, edited by Akira Iwata, KK. Triceps, Nov. 13, 1998.

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