Variable delay unit for data synchronizer using phase-sensitive

Details Variable delay unit for data synchronizer using phase-sensitive Variable delay unit for data synchronizer using phase-sensitive

1982-09-23

1985-06-18

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

328 63, 328 72, H04L 704

Patent

active

045244480

ABSTRACT:
A signal processing circuit for a signal varying in its properties, e.g., in its degress of distortion, in which the input signal is fed in parallel to two similar processing circuits e.g., equalizers, the characteristic of which can be varied by a control signal, wherein the control signal from the one processing circuit is periodically varied and the output signal is fed to a detector circuit which in optimum signal processing emits a trigger pulse to a holding circuit 52 which stores the corresponding control signal level, which is fed to the second processing circuit.
A variable delay unit for the data is controlled by a continuously varying up-down counter, the contents of which continuously vary at the rate of a high frequency clock pulse. The direction of count and the time of the count is controlled by comparing the relative time-positions or phases of a timing pulse received with the data and a timing pulse generated at the receiver.

REFERENCES:
patent: 3745248 (1973-07-01), Gibson
patent: 4119796 (1978-10-01), Jones
patent: 4131856 (1978-12-01), Chapman
patent: 4191975 (1980-03-01), White et al.

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