Variable delay line phase-locked loop circuit synchronization sy

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307262, 328 55, 328 63, 328 72, 328155, H03K 513, H03K 500

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active

051011174

ABSTRACT:
A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.

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