Variable delay CMOS circuit with PVT control

Details Variable delay CMOS circuit with PVT control Variable delay CMOS circuit with PVT control

2001-02-28

2003-02-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000

Reexamination Certificate

active

06522185

ABSTRACT:

TECHNICAL FIELD
The present disclosure is generally related to electronic digital logic circuitry affecting signal sensitivity or transmission integrity and, more particularly, to a method and apparatus for variably controlling the propagation delay of a binary signal.
BACKGROUND
“CMOS” is an acronym for the Complementary Metal Oxide Semiconductor. As the name implies, CMOS devices are formed using metal conductors, oxide insulators, and “semiconductors.” Semiconductors are crystalline materials having electrical properties between that of a conductor and an insulator. The conductivity of semiconductor material can be precisely controlled in a process called “doping” where a small amount of “dopant” is added to an otherwise pure, or “intrinsic,” semiconductor material. Doping leaves behind mobile, charged carriers for conducting electricity in the otherwise electrically-neutral semiconductor crystal lattice. When intrinsic semiconductor materials are doped so as to add negative charge carriers to the lattice, the material is referred to as an “n-type,” or donor “extrinsic” semiconductor, while the addition of positive carriers creates a “p-type,” acceptor material.
A “transistor” is one particular type of semiconductor device that is noteworthy for its ability to operate as an electrical switch or amplifier, depending upon its configuration. There are two basic types of transistors—bipolar (or junction) transistors and field-effect transistors (“FETs”). Although equivalent digital circuits can be created using either transistor technology, FET technology is often preferred and will be used for the various examples described here.
The term “field-effect” is related to the application of an “electromotive field,” or voltage, to a “gate” terminal connected near the “junction” of the p-type and n-type materials. This gate voltage controls the size of a conductive “channel” through which electrons must flow through as they pass from the “source” terminal to the “drain” terminal, or vice versa. Consequently, the gate voltage can be used to control the source-drain current through the channel in an FET.
Metal-oxide FETs, or “MOSFETs,” have an additional layer of a non-conductive oxide material (such as silicon dioxide) that insulates the gate terminal from the channel. Consequently, the gate current is very small regardless of the applied voltage so that circuits using MOSFETs can be made to consume, or “dissipate,” very little power. MOSFETs are characterized by their mode of operation and whether the channel is made from an n- or p-type semiconductor material. “Depletion-mode” operation occurs when the gate-source voltage (between the gate and source terminals) is used to deplete the channel of free carriers so as to reduce the size of the conductive channel and increase its resistance. In contrast, “enhancementmode” operation occurs when the gate voltage is chosen to increase the size of the channel and thus decrease the source-drain resistance. Enhancement-mode MOSFETs are generally preferred, however, because the device will be normally “off” (i.e., the source drain resistance will be high) when the gate voltage falls below a certain “threshold value.”
Nonetheless, even when the gate voltage is low enough to turn “off” an enhancement-mode MOSFET, the resistance between the source and drain terminals is still generally not large enough to prevent current from flowing between the source and drain under a large source-drain voltage. Consequently, as shown in
FIG. 1
, a MOSFET
5
is typically arranged in a digital circuit
10
with a resistor Rd, where G, D, S refer to the gate, source, and drain terminals. In addition, the source terminal is usually grounded in order to provide a reference voltage (of zero volts) with regard to the applied voltage at the drain Vdd.
In
FIG. 1
, the broken line inside the MOSFET
5
indicates that the transistor operates in enhancement mode and is therefore normally off (when Vin is zero). It will also be noted the source and substrate terminals are internally connected in the MOSFET symbol that is used in FIG.
1
. However, depletion-mode and/or enhancement-mode MOSFETs with external and/or no connections between the source and substrate terminals may also be used. The direction of the arrow indicates whether the source and drain are connected by an n-type inversion layer as shown in
FIG. 1
, or a p-type inversion layer where the arrow is reversed. The MOSFET
5
is also equivalently represented with the circular “envelope” removed.
In the circuit configuration shown in
FIG. 1
, the resistor Rd will act as a voltage divider when the transistor is conducting (and current is flowing between the source and drain) so as to prevent the transistor from receiving large currents. Consequently, when an input voltage Vin (that is larger than the threshold value) is applied to the gate terminal G, current will flow through Rd to create a corresponding low output voltage Vout near the gate terminal. Similarly, when input voltage Vin is removed, Vout will return to nearly the value of Vdd. For gate voltages that are between the threshold voltage and ground, the device will partially conduct, and thus act essentially as a variable resistor.
The direction of the source drain current will depend upon the polarity of the applied voltages as is well known in the art. However, since the output voltage Vout is opposite to the input voltage Vin, this simple digital circuit is called an “inverter.” Of course, “on” and “off” are relative terms that depend on the configuration of the applied voltages. Therefore, switching from any state to the another state is often more-generally referred to as “actuating” from an “asserted” state to a “deasserted” state.
The resistor Rd in
FIG. 1
is referred to as a “passive load” because its power-consumption effect on the circuit does not change.
FIG. 2
illustrates another inverter configuration
20
where the passive resistor Rd is replaced with another n-type enhancement MOSFET
5
that actuates, and thus provides full resistance, when Vdd is high. This second digital circuit configuration for an inverter shown in
FIG. 2
is generally preferred because it is smaller and easier to fabricate than the one shown in FIG.
1
.
FIG. 3
illustrates yet another embodiment of a conventional MOSFET inverter
30
including an (upper) p-type enhancement MOSFET
7
and a (lower) n-type enhancement MOSFET
5
. The p-type enhancement-mode MOSFET
7
is “complementary” to the n-type MOSFET
5
device in that all voltages and currents are reversed from the n-type device
5
. Consequently, replacing one of the n-MOSFETS in the inverter
20
in
FIG. 2
with a p-MOSFET creates a Complementary Metal-Oxide Semiconductor, or “CMOS,” inverter
30
where when one device is on, the other is off, and vice-versa. The basic CMOS inverter can be modified to build other complementary circuits as described below.
For example, the inputs and outputs of two of the CMOS inverters
30
shown in
FIG. 3
can be connected in series to create the uni-directional “driver”
40
shown in FIG.
4
. The driver
40
is also referred to as a “uni-directional CMOS transmission gate,” or “buffer.” Since there are two inverters in series, Vout in this device will follow Vin. However, due to the inherent “capacitance,” or ability to store energy in the form of opposite charges (e.g., that are segregated in the different layers of material) in each of the transistors, each inverter
30
will require a small period of time before it fully changes the state of its charge. Thus, the inputs and outputs for several inverters
30
can be “cascaded” to create a delay between the time that Vout changes in response to Vin. Furthermore, increasing Vdd relative to ground will reduce this “signal propagation delay,” and vice versa. However, increasing Vdd also increases energy dissipation and reliability concerns due to increased oxide breakdowns, hot-electrons, and other effects that should be avoided. Signal propagation delay in cascaded CMOS inverters is further discussed in Rabey,

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