Variable delay clock synthesizer

Details Variable delay clock synthesizer Variable delay clock synthesizer

2007-09-25

2007-09-25

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S149000

Reexamination Certificate

active

11284518

ABSTRACT:
In an embodiment, a fine resolution of variable clock delay is implemented using a variable DC offset having fine resolution. The proportional ratio between the DC offset and the phase delay/advance of the clock is calibrated in a closed-loop manner. In another embodiment, in a calibration circuit, an adaptive positive DC offset is added to the output of a delay buffer to advance the phase of the clock output, which also has a phase delay from the delay buffer. The DC offset is adjusted in a closed-loop manner to make the phase advance, due to the DC offset, compensate for the phase delay, due to the delay buffer. Once the phase relationship of the DC offset to the clock phase advance is calibrated, the DC offset can be scaled and added to the output of another buffer of the same type to achieve a desired phase delay or advance of the clock signal.

REFERENCES:
patent: 6707330 (2004-03-01), Nakanishi
patent: 7038511 (2006-05-01), Kim et al.
patent: 7076013 (2006-07-01), Cho
Mark G. Johnson, et al.,A Variable Delay Line PLL for CPU-Coprocessor Synchronization; IEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1998.
Stefanos Sidiropoulos et al.,A Semidigital Dual Delay-Locked Loop; IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997.

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