Variable delay clock circuit and method thereof

Details Variable delay clock circuit and method thereof Variable delay clock circuit and method thereof

2008-07-29

2008-07-29

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S291000

Reexamination Certificate

active

11517415

ABSTRACT:
An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.

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