Variable delay clock circuit

Details Variable delay clock circuit Variable delay clock circuit

1992-04-29

1993-11-16

Callahan, Timothy P.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307603, 307608, 307320, H03K 513, H03K 5159, H03K 1728

Patent

active

052626903

ABSTRACT:
A high-speed clock delay circuit in which an external differential digital clock signal is connected to a pair of differentially connected, current switching transistors. Emitter follower drivers couple the switching transistors to differential delayed clock output terminals. A pair of diodes cross-coupled between the differential output terminals and the switching transistors provide a relatively large Miller Effect capacitance, the charging and discharging of which provides a delay in the switching of the transistor pair, as measured differentially. Changing the charging and discharging current through the emitter follower driver, changes the bias across the diodes and thus changes their effective capacitance.

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