Variable delay circuit including current mirror and ramp generat

Details Variable delay circuit including current mirror and ramp generat Variable delay circuit including current mirror and ramp generat

1995-04-28

1996-10-29

Psitos, Aristotelis

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

G11B 509

Patent

active

055702430

ABSTRACT:
A variable delay circuit, known as a delayed read data single shot (DRDSS) circuit, adapted for use in a data read channel which reads signals recorded with different clock frequencies in different zones on a data storage device, wherein the read channel includes a variable oscillator whose reactive impedance is supplied with a charging current whose level corresponds to the clock frequency of the zone being read. A current duplicator produces an output current that is a substantially identical duplicate of the charging current to provide an output level as a function of that output current, this output level being compared to a ramp signal, whereby a delayed version of the signal read from the data storage device is produced when the ramp signal is substantially equal to the output level. The ramp signal is generated by a ramp generator having a reactive impedance that is substantially identical to the reactive impedance of the variable oscillator, and that is charged when a signal is read from the data storage device.

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