Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2001-05-14
2002-10-15
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S136000, C327S281000
Reexamination Certificate
active
06466076
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a variable delay circuit having a ramp voltage generating unit, and more particularly to a high-performance variable delay circuit which generates delay times following the settings with excellent linearity.
(b) Description of the Related Art
In recent years, capability of higher time resolution measurement has been required of LSI testers along with the higher speed operation of LSIs to be measured. The minimum time resolution (1 LSB) is on its way to falling below 10 pico-second (ps). Moreover, LSI testers for measuring LSI absolute performance must have a sufficiently high accuracy guaranteed. Typically, the degree of accuracy requirements for the time resolution is 1 LSB or smaller. The variable delay time used for the time resolution measurement is generated by a known variable delay circuit having a ramp voltage generating unit. For the sake of sufficiently high accuracy, the linearity of the delay time with respect to settings is of importance. Since the linearity of the delay time depends on the linearity of the ramp voltage waveform, it is important to generate the ramp voltage with superior linearity. As used herein, the term “ramp voltage” refers to a signal voltage having a waveform wherein the amplitude varies or changes linearly in proportion to time.
FIG. 1
is a circuit diagram of a variable delay circuit described in Japanese Patent Laid-Open Publication No. Hei 8-181584. Nodes N
11
and N
12
receive differential signals which are complementary to each other. It is assumed here that the logic on the node N
11
is the positive logic. A node N
19
receives an arbitrary voltage setting which falls within the range of the amplitude on a ramp voltage generating node
16
. When H-level and L-level are input to the node N
11
and the node N
12
, respectively, an NPN transistor Q
11
turns ON and an NPN transistor Q
12
turns OFF. As a result, a node N
13
turns to H-level. Thus, an NPN transistor Q
13
turns ON to charge a storage capacitor C
11
, thereby raising the potential of the node N
16
to H-level. The storage capacitor C
11
is charged steeply in a very short time after the potential change of the node N
13
due to the large driveability of the NPN transistor Q
13
.
Feed of L-level to the node N
11
and H-level to the node N
12
turns the NPN transistor Q
11
OFF and the NPN transistor Q
12
ON. Thus, the node N
13
turns to L-level. Here, the NPN transistor Q
13
turns OFF since the node N
16
is held at the H-level by the charge stored in the capacitor. The charge stored in the storage capacitor C
11
is gradually discharged at a constant rate through a constant-current source
15
. Due to the constant rate of the discharge, the potential of the node N
16
traces a ramp voltage waveform which declines linearly in proportion to time. When the ramp voltage falls below the potential input to the node N
19
, a comparator
16
turns its output potential on a node N
17
from H-level to L-level. The voltage setting input to the node N
19
can be changed to modify the time instant at which the potential of the ramp voltage falls below the potential input to the node N
19
. The voltage setting for the node N
19
achieves variation of the delay time.
FIG. 2
shows potential changes on some of the nodes in the circuit diagram of FIG.
1
. For convenience of description, the delay variation is shown in seven levels. It is to be noted however that the known high-performance variable delay circuits usually have a greater number of variation levels.
The node N
19
receives any one of arbitrary voltage settings V
1
to V
7
. The potential of the node N
17
falls from H-level to L-level at any of the time instants t
1
to t
7
at which the potential of the node N
16
falls below the potential of the node N
19
. The time interval between the time t
0
at which the node N
11
falls and any one of the times t
1
to t
7
at which the node N
17
falls based on the voltage settings V
1
to V
7
is the delay time generated by the variable delay circuit. The time interval between the time t
1
and the time t
7
is the span of the variable delay time.
In the variable delay circuit described in the above publication, as described above, the charge stored in the storage capacitor C
11
is discharged through the constant-current source
15
. In the discharge, the waveform of the node N
13
does not trace an ideal rectangular waveform and falls from H-level to L-level with a significant deformation (deterioration). Thus, during the potential fall of the node
16
, the capacitor-charging transistor Q
13
is subjected to a voltage that varies with time, across its base and emitter. It is to be noted that there is a parasitic capacitance Cje
11
between the base and emitter of the capacitor-charging transistor Q
13
, which means that the voltage across this parasitic capacitance Cje
11
varies also. The variation of the voltage across the parasitic capacitance Cje
11
causes storage of charge in this parasitic capacitance. This impedes the charge in the storage capacitor C
11
from decreasing at a constant rate, thereby degrading the linearity of the ramp voltage. The waveform shown in
FIG. 2
has a significant deterioration in the linearity thereof. In this connection, the straight, broken line in
FIG. 2
shows a ramp voltage without any linearity deterioration that results from the storage of charge in the parasitic capacitance Cje
11
of the capacitor-charging transistor Q
13
.
FIGS. 3A and 3B
are a graph showing the characteristic of the delay time generated by the variable delay circuit of
FIG. 1 and a
graph showing the amount of deterioration of the delay time from the straight line, respectively. The delay time loses its linearity while the potential of the node N
13
in
FIG. 1
changes from H-level to L-level.
FIG. 4
shows how the ramp voltage in the variable delay circuit shown in
FIG. 1
deteriorates in linearity due to the parasitic capacitance, illustrating (a) potential of the node N
13
, (b) base-to-emitter voltage of the transistor Q
13
, (c) charge in the parasitic capacitor Cje
11
and (d) potential of the node N
16
. The diagram specifically shows the time interval from the time instant t
0
when the waveform of the node N
13
starts its fall to the time instant tm when the waveform of the node N
13
completes the change to L-level, during which the charge flows on the node
16
into the parasitic capacitance Cje
11
of the capacitor-charging transistor Q
13
to cause a deterioration in the linearity of the ramp voltage. The voltage across the parasitic capacitance Cje
11
continues to change until the ramp voltage reaches L-level. A linear change of the voltage, however, results in a linear outflow of the charge in the parasitic capacitor Cjell through the constant-current source
15
after the time instant tm, thereby causing no significant deterioration in this period in the linearity of the ramp voltage.
Among the possible prevention measures against the linearity deterioration, a method may be adopted by forming the storage capacitor C
11
to have a larger capacitance and increasing the current flowing through the constant-current source
15
so that the influence of the charge flow into the parasitic capacitance Cje
11
of the capacitor-charging transistor Q
13
decreases in the proportion to the whole current. If the measure by this method is adopted, however, the upsizing of the capacitor causes an increase in circuit scale, and the rise of the current yields an increase in power dissipation. Higher integration and multi-function of LSIs in the trend of recent years increase the numbers of pins on the LSIs to be measured and advance the measurement coverage. This trend also necessitates higher integration and lower power dissipation even in the tester LSIs. In light of these requirements, the increases in circuit scale and power dissipation are unacceptable. Furthermore, this measure provides merely a reduction of the proportion of deterioration to the whole, and the
Cox Cassandra
Wells Kenneth B.
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