Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2005-02-01
2005-02-01
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S284000
Reexamination Certificate
active
06850107
ABSTRACT:
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.
REFERENCES:
patent: 4255790 (1981-03-01), Hondeghem
patent: 4458165 (1984-07-01), Jackson
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5336939 (1994-08-01), Eitrheim et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5600274 (1997-02-01), Houston
patent: 5663665 (1997-09-01), Wang et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5717353 (1998-02-01), Fujimoto
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 5844954 (1998-12-01), Casasanta et al.
patent: 5909133 (1999-06-01), Park
patent: 5946268 (1999-08-01), Iwamoto et al.
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6016282 (2000-01-01), Keeth
patent: 6066969 (2000-05-01), Kawasaki et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6087868 (2000-07-01), Millar
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6104224 (2000-08-01), Koshikawa
patent: 6137334 (2000-10-01), Miller, Jr. et al.
patent: 6173424 (2001-01-01), Voshell et al.
patent: 6173432 (2001-01-01), Harrison
patent: 6175605 (2001-01-01), Chi
patent: 6175928 (2001-01-01), Liu et al.
patent: 6177823 (2001-01-01), Saeki
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6201752 (2001-03-01), Bui et al.
patent: 6230245 (2001-05-01), Manning
patent: 6255880 (2001-07-01), Nguyen
patent: 6317381 (2001-11-01), Gans et al.
patent: 6327196 (2001-12-01), Mullarkey
patent: 6349399 (2002-02-01), Manning
patent: 6359482 (2002-03-01), Miller, Jr. et al.
patent: 6392458 (2002-05-01), Miller, Jr. et al.
patent: 6407687 (2002-06-01), Martin et al.
patent: 6417713 (2002-07-01), DeRyckere et al.
patent: 6446226 (2002-09-01), Voshell et al.
patent: 6449727 (2002-09-01), Toda
patent: 6470060 (2002-10-01), Harrison
patent: 6476653 (2002-11-01), Matsuzaki
patent: 6486723 (2002-11-01), DeRyckere et al.
patent: 6493829 (2002-12-01), Kubo
patent: 6499111 (2002-12-01), Mullarkey
patent: 6518800 (2003-02-01), Martin et al.
patent: 6556489 (2003-04-01), Gomm et al.
patent: 6586979 (2003-07-01), Gomm et al.
Garlepp, Bruno W. et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, pp. 632-644, May 1999.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nu Ton My-Trang
LandOfFree
Variable delay circuit and method, and delay locked loop,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable delay circuit and method, and delay locked loop,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable delay circuit and method, and delay locked loop,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3508301