Variable delay circuit and method, and delay locked loop,...

Details Variable delay circuit and method, and delay locked loop,... Variable delay circuit and method, and delay locked loop,...

2002-10-15

2004-07-06

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C713S401000

Reexamination Certificate

active

06759883

ABSTRACT:

TECHNICAL FIELD
The invention relates clock circuits, and, more particularly, to a circuit and method for providing a clock signal with a variable delay in a manner that uses relatively little circuitry.
BACKGROUND OF THE INVENTION
Variable delay circuits for delaying digital signals are in common use in a wide variety of integrated circuit devices. For example, variable delay circuits are commonly used as part of delay locked loops in integrated circuit memory devices. An example of a conventional variable delay circuit
10
is shown in FIG.
1
. The variable delay circuit
10
includes a series of inverters
12
a, b, c, d, e
, the first of which
12
a
receives a clock signal CLK. The output of each inverter
12
a, b, c, d, e
is coupled to a respective pass gate
16
a, b, c, d, e
that are selectively enabled by respective stages of a shift register
18
. Only one of the stages of the shift register stores a logic “1”, and all of the other stages store a logic “0”. The pass gate
16
a, b, c, d, e
that receives the logic “1” is enabled while the remaining pass gates
16
a, b, c, d, e
that receive a logic “0” are disabled. The logic “1” is shifted to the right by applying a shift pulse to a DELAY INCR input of the shift register
18
, and is shifted to the left by applying a shift pulse to a DELAY DECR input of the shift register
18
. Outputs of all of the pass gates
16
a, b, c, d, e
are coupled to each other to generate a delayed clock signal at a CLK-OUT terminal.
In operation, one of the pass gates
16
a, b, c, d, e
is enabled by receiving a logic “1” from the shift register
18
, thereby coupling the output from the respective inverter
12
a, b, c
, to the CLK-OUT terminal. The magnitude of the delay of the CLK-OUT signal is adjusted by shifting the logic “1” right and left by applying a shift pulse to the DELAY INCR input or DELAY DECR input, respectively, of the shift register
18
.
Although the variable delay circuit
10
of
FIG. 1
provides adequate performance under some circumstances, it has the significant disadvantage of inverting the clock signal as the delay is switched from one inverter
12
a, b, c, d, e
to the next. More specifically, for example, when the logic “1” is shifted from the pass gate
16
b
to the pass gate
16
c
, the delay of CLK-OUT signal shifts by not only the additional delay of the inverter
12
c
, but, because of the additional inversion caused by passing though the inverter, an additional delay of one-half the period of the CLK signal. This additional delay can be a significant problem in some applications.
The above-described problem with the conventional variable delay circuit
10
is well recognized, and has been solved to some extent by using a variable delay circuit
30
as shown in FIG.
2
. The variable delay circuit
30
uses many of the same components used in the variable delay circuit
10
of
FIG. 1
, and these components have been provided with the same reference numerals. The delay circuit
30
differs from the delay circuit
10
by including an additional series of inverters
32
a, b, c, d, e
, the first of which
32
a
receives CLK*, which is the compliment of the CLK signal. The connections to the pass gates
16
a, b, c, d, e
then alternate between the inverters
12
a, b, c, d, e
and the inverters
32
a, b, c, d, e
so all of the pass gates
16
a, b, c, d, e
receive the same phase of the clock signal. As a result, when the logic “1” is shifted from one pass gate
16
a, b, c, d, e
to the next, the delay of the CLK-OUT signal varies by only the delay of the additional inverter
12
or
32
.
Although the variable delay circuit
30
avoids the major problem with the delay circuit
10
, it does so at the expense of doubling the number of required inverters. The extra circuitry and consequent expense of these additional inverters can be significant, particularly where a large number of inverters are need to provide a large delay or a large number of delay increments.
There is therefore a need for a variable delay circuit that avoids the problem of inverting the clock signal from one stage to the next, but does so in a manner that does not require a doubling of the number of inverters needed to achieve a desired delay or a number of delay increments.
SUMMARY OF THE INVENTION
A variable delay circuit produces a delayed clock signal from an input clock signal by coupling the input clock signal through a plurality of inverting logic circuits arranged in series with each other. A delay select circuit, such as a shift register, receives at least one delay command signal indicative of a delay of the variable delay circuit. The delay select circuit then generates at least one control signal responsive to the delay command signal. The variable delay circuit also includes a clock transfer control circuit coupled to the inverting logic circuits and the delay select circuit. The clock transfer control circuit receives the input clock signal and adjusts the delay of the delayed clock signal responsive to the at least one control signal. The delay is adjusted by varying the number of inverting logic circuits through which the input clock signal is coupled between the clock input terminal and the clock output terminal. The clock transfer control circuit also adjusts the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal so that the correct polarity of the delayed clock signal is maintained despite being coupled through a variable number of inverting logic circuits.


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