Oscillators – Ring oscillators
Reexamination Certificate
2002-12-20
2004-04-20
Pascal, Robert (Department: 2817)
Oscillators
Ring oscillators
C327S278000
Reexamination Certificate
active
06724268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a phase locked loop (PLL) suited for portable electronic devices and more specifically to a differential voltage-controlled delay circuit usable in a differential voltage-controlled oscillator for use in such PLLs.
2. Description of the Prior Art
Ring oscillators have come to attract engineer's attentions as the voltage-controlled oscillator (VCO) for use in PLLs. This is because ring oscillators have a wider oscillation range covering a GHz order and are suitable for monolithic integration, which enables a reduction in the size of integrated circuit (IC) chip.
As the degree of integration becomes higher, IC patterns are further miniaturized, which lowers the withstand voltages of circuit elements constituting the IC. For this reason, desired is ring oscillators and PLLs that can operate with a lower power supply voltage. Also, in order that ring oscillators or PLLs can be used in portable electronic devices, which are usually provided with a lower power battery, it is preferable that ring oscillators are low in power consumption.
FIG. 1
is a circuit diagram showing an exemplary arrangement of a typical voltage-controlled ring oscillator disclosed in U.S. Pat. No. 5,418,499. In
FIG. 1
, the ring oscillator
102
is constituted by connecting an odd number of (3 in this specific example) variable-delay inverters
120
-
1
,
120
-
2
and
120
-
3
in the form of a ring. Each variable-delay inverter
120
-
i
(i=1, 2, 3) comprises p-channel MOS FETs (metal oxide semiconductor field-effect transistors) (referred to as “pMOS transistors”) TP
2
and TP
1
and n-channel MOS FETs (referred to as “nMOS transistors”) TN
1
and TN
2
serially-connected (so-called totem pole-connected) between a power supply line L
1
and a ground line L
2
.
The pMOS transistor TP
1
and the nMOS transistor TN
1
of which the gates and the drains are connected together to form a CMOS (complementary MOS) inverter are referred to as “switch elements TP
1
and TN
1
”, respectively. The pMOS transistor TP
2
and the nMOS transistor TN
2
are referred to as “current-control elements TP
2
and TN
2
”, respectively.
The input and output terminals of the CMOS inverter comprised of the switch elements TP
1
and TN
1
serve as the input and the output terminals of each variable-delay inverter
120
-
i
. A first control voltage Vc
1
is applied in common to the current-control element TP
2
of each inverter
120
-
i
, and a second control voltage Vc
2
is applied in common to the current-control element TN
2
of each inverter
120
-
i.
FIG. 2
is a diagram showing an equivalent circuit of a variable-delay inverter
120
-
i
to illustrating the operational principle of the voltage-controlled ring oscillator
102
. In
FIG. 2
, the equivalent circuit comprises a one-stage variable-delay inverter
120
-
i
and an equivalent capacitor Cin inserted between the output terminal Vo of the inverter
120
-
i
and the ground line VG and equivalent to the input capacitance of the next stage variable-delay inverter
120
.
First, it is assumed that the two current-control elements TP
2
and TN
2
are completely on having the ground voltage VG applied as the first control voltage Vc
1
and the power voltage VD applied as the second control voltage Vc
2
. Then, if the input Vi of the variable-delay inverter
120
is high or at the power supply voltage VD, the switch element TP
1
is off and the switch element TN
1
are on resulting in the output of the variable-delay inverter
120
being low or at the ground voltage VG.
In this state, if the input voltage Vi changes from the high level to the low level, then the switch element TP
1
turning on and the switch element TN
1
turning off causes the equivalent capacitor Cin to be charged through the current-control element TP
2
and the switch element TP
1
, which results in the high level of the output voltage Vo. The charge current in this case is controlled by the current-control element TP
2
and the first control voltage Vc
1
.
In this state, if the input voltage Vi changes from the low level to the high level, then the switch element TP
1
turning off and the switch element TN
1
turning on causes the equivalent capacitor Cin to be discharged through the switch element TN
1
and the current-control element TN
2
, which results in the low level of the output voltage Vo. The discharge current in this case is controlled by the current-control element TN
2
and the second control voltage Vc
2
.
More specifically, as shown in
FIG. 3
, if the input voltage Vi changes from the high level to the low level at time t1, then, with a certain delay after the input voltage Vi change, the output voltage Vo begins to change (rise in this case) at time t2. In this case, the larger the first control voltage Vc
1
is, the smaller the gate-source voltage of the current-control element TP
2
, resulting in a smaller charging current. Thus, as the first control voltage Vc
1
increases in magnitude, the change in the output voltage Vo or the waveform of voltage across the equivalent capacitor Cin varies as shown by waveforms labeled “a”, “b” and “c”.
Similarly, if the input voltage Vi changes from the low level to the high level at time t3, then, with a certain delay after the input voltage Vi change, the output voltage Vo begins to change (fall in this case) at time t4. In this case, the smaller the second control voltage Vc
2
is, the smaller the gate-source voltage of the current-control element TN
2
, resulting in a smaller charging current. Thus, as the second control voltage Vc
2
decreases in magnitude, the change in the output voltage Vo or the waveform of voltage across the equivalent capacitor Cin varies as shown by waveforms labeled “d”, “e” and “f”.
That is, with a larger first control voltage Vc
1
and/or a smaller second control voltage Vc
2
, it takes the longer delay time for the output voltage to reach a threshold level to turn to the inverted level after the inversion of the input voltage Vi level.
Thus, in each variable-delay inverter
120
-
i
, the rising characteristic of the output voltage Vo varies depending on the first control voltage Vc
1
, and the falling characteristic of the output voltage Vo varies depending on the second control voltage Vc
2
, which causes a change in the propagation delay of each variable-delay inverter
120
-
i
and accordingly in the oscillation frequency of the ring oscillator
102
.
However, in the above-described voltage-controlled ring oscillator
102
, a lowering of the power supply voltage VD decreases the charging and discharging currents that flow during a period of inversion of the output voltage, which lowers the oscillation frequency. If the power supply voltage VD becomes too low to keep the gate-source voltages at a level necessary for turning on the switch elements TP
1
and TN
1
and the current-control elements TP
2
and TN
2
, then the voltage-controlled ring oscillator
102
ceases oscillation.
Also, in the above-described ring oscillator
102
, which includes four serially connected transistors, two of the four transistors have to be turned on at a time. In order to maintain an enough gate-source voltage, the power supply voltage cannot be lowered so much.
One of the solutions to this problem is provided by Japanese unexamined patent publication No. Hei10-200382 entitled “Voltage Controlled Oscillator Circuit for Low Voltage Driving”. This voltage controlled oscillator circuit comprises a ring oscillator portion consisting of three 2-transistor inverters and an oscillation frequency controller for providing a power supply voltage to the ring oscillator portion. That is, the oscillation frequency is controlled by controlling the power supply voltage to the ring oscillator portion. Since the parasitic capacitance of the MOS FET gate is on the order of several to tens fF (femtofarad), if it is assumed that the gate capacitance is 10 fF, the oscillation frequency controller output (i.e., the power supply voltage to the ring oscillator portion) is
Chang Joseph
Pascal Robert
Posz & Bethards, PLC
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