Variable delay circuit and delay time setting method therefor

Details Variable delay circuit and delay time setting method therefor Variable delay circuit and delay time setting method therefor

1999-11-26

2001-07-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S271000

Reexamination Certificate

active

06259294

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable delay circuit built in a semiconductor device and a delay time setting method for the variable delay circuit, and particularly relates to a variable delay circuit having a reduced number of elements and a reduced chip area and a delay time setting method for the variable delay circuit.
2. Description of the Related Art
A conventional variable delay circuit is described in, for example, Japanese Patent Unexamined Application Publication No. 9-46195 (to be referred to as “Publication 9-461951, ” hereinafter).
FIG. 1
is a circuit diagram showing the conventional variable delay circuit described in the Publication 9-46195 and
FIG. 2
is a circuit diagram showing the structure of a transfer gate shown in FIG.
1
.
In the conventional variable delay circuit described in the Publication 9-46195, (n+1) (where n is an integer equal to 1 or higher) inverters I
1
, I
2
, . . . and In+1are connected in series as shown in FIG.
1
. The output resistance is almost constant among the inverters I
1
, I
2
, . . . and In+1. Transfer gates S
1
, S
2
, S
3
, . . . and Sn and capacitive elements C
1
, C
2
, C
3
, . . . and Cn are connected in series between the nodes of adjacent inverters and a ground potential, respectively. The capacity is almost constant among the capacitive elements C
1
, C
2
, C
3
, . . . and Cn. The variable delay circuit is also provided with a selection circuit section
101
having output terminals D
1
, D
2
, D
3
, and . . . Dn. The output terminals D
1
, D
2
, D
3
, . . . and Dn are connected to the control terminals of the transfer gates S
1
, S
2
, S
3
, . . . and Sn, respectively. A controlling signal (binary code signal) indicating the number of transfer gates S
1
, S
2
, S
3
, . . . and Sn to be simultaneously turned on is inputted to the input terminal of the selection circuit section
101
.
Each transfer gate is provided with a P-channel MOS transistor Q
103
and an N-channel MOS transistor Q
102
as shown in FIG.
2
. An inverter IV
102
is connected between the control terminal and the gate of the P-channel MOS transistor Q
103
. The binary signal inputted to the control terminal is, therefore, inputted to the gate of the N-channel MOS transistor Q
102
as it is, and inputted to the P-channel MOS transistor Q
103
after being inverted. In this way, the on/oft controlling of the P-channel MOS transistor Q
103
and the N-channel MOS transistor Q
102
is conducted.
In the conventional variable delay circuit constituted as stated above, if the value of n is 3, since output resistances R
1
, R
2
, R
3
and R
4
of the inverters I
1
, I
2
, I
3
and I
4
, respectively, are almost constant and the capacities of the capacitive element C
1
, C
2
, C
3
and C
4
are almost constant, delay time Trc determined by a time constant &tgr;=RC is almost constant, as well. The capacity of the capacitive element is set quite small and the output resistance R is set at about 100&OHgr; so as to satisfy the relationship represented by (delay time Trc)<<(propagation delay time Tin of inverter). Thus, the delay time between {(n+1)×Tin} and {(n+1)×Tin+n×Tc} can be arbitrarily adjusted with a delay time Trc as a minimum unit. Although Tc is considered to be defined as the propagation delay time of a capacitive element, Publication 9-46195 makes no mentions thereof.
Nevertheless, the above-stated conventional variable delay circuit is provided with the transfer gates controlling the connection between capacitive elements and the ground respectively in addition to the series connected inverters and the capacitive elements connected between the output terminals of the inverters and the ground potential, respectively. Due to this, enormous number of transfer gate elements are provided in a circuit designed to process address signals, data input signals and the like and requiring many variable delay circuits which function to adjust delay time. As a result, the area of a chip incorporating such variable delay circuits disadvantageously increases.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a delay circuit and a delay time setting method therefor, capable of reducing the number of elements of a product requiring a plurality of unit delay circuits and suppressing a chip area from increasing.
According to one aspect of the present invention, a variable delay circuit comprises a plurality of unit delay circuits connected in series. Each of the plurality of unit delay circuits includes an inverter and a transistor having a current control electrode connected to an output terminal of the inverter. The transistor generates a first delay and a second delay relating to a signal supplied to another electrode. The second delay is larger than the first delay. The variable delay circuit further comprises a selection control circuit which selects a signal applied to the another electrode of each of a plurality of the transistors.
According to the present invention, the capacity of the transistor is varied by switching a signal supplied to the another electrode of the transistor. Therefore, it suffices to provide only the transistors as elements provided between the inverters and the selection control circuit. It is, therefore, possible to greatly reduce the number of elements. It is thereby possible to make a circuit requiring many unit delay circuits small in size. Besides, the stability of the operation of the circuit enhances.
If it is assumed, for example, that the capacity between the gate and back bias of an MOS transistor is Cgb, that between the gate and source thereof is Cgs and that between the gate and drain is Cgd, then it is possible to obtain a time constant &tgr;=R×(Cgb+Cgs+Cgd) from the sum R of the ON resistance and wiring resistance of a CMOS inverter. The capacities Cgs and Cgd can be controlled by switching levels of source and drain potentials to the logic levels of HIGH potential/LOW potential. To realize the delay time determined by this time constant &tgr;, the variable delay circuit according to the present invention is constituted by extremely small number of elements.
According to another aspect of the present invention, a delay time setting method comprises the steps of: conducting a test for a circuit including the variable delay circuit; setting a delay amount of each of the unit delay circuits based on a result of the test. The later step includes the step of setting switching elements so that different potentials from each other are supplied to two electrodes other than the current control electrode in a unit delay circuit whose delay amount has been set to the first delay and to two electrodes other than the current control electrode in a unit delay circuit whose delay amount has been set to the second delay.


REFERENCES:
patent: 5631593 (1997-05-01), Molin
patent: 62-120117 (1987-06-01), None
patent: 5-308260 (1993-11-01), None
patent: 8-032421 (1996-02-01), None
patent: 9-046195 (1997-02-01), None
patent: 9-180491 (1997-07-01), None
patent: 10-163822 (1998-06-01), None

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