Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-11-27
2004-09-14
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S277000
Reexamination Certificate
active
06791389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable delay circuit and a testing apparatus for a semiconductor circuit.
2. Description of the Related Art
Recently, a delay error due to signal transmission path of a delay circuit used for a semiconductor testing apparatus cannot be ignored as operation speed of semiconductor circuits become faster. Further, a variable delay circuit of fine resolution requires to have large volume of control table, which causes the volume of delay circuit to become larger. Therefore, it is being demanded to achieve efficient control of the variable delay circuit.
FIG. 1
shows a conventional variable delay circuit
50
. The conventional variable delay circuit
50
has a plurality of delay circuit units
22
, a table
42
and a plurality of switches
32
. A delay setting value
12
, which is required delay amount provided from outside (by a user), is inputted to the table
42
. And, an input signal
10
is inputted to a first stage delay circuit unit
22
a
from the outside.
The plurality of delay circuit units
22
respectively has two signal transmission paths, one of which is selected by the switches
32
provided.
The table
42
outputs data for controlling the path changing switches
32
of the delay circuit units
22
in response to the delay setting value
12
. The table has data amounts determined by the delay amount of the variable delay circuit
50
, delay resolution and the number of stages of the delay circuit units
22
. For example, in case the variable delay amount is 8 ns, delay resolution is 125 ps (or 64 gradations) and the number of stages is n stages, a table having data width of 6 (for addressing)+n (for selecting a path at each stage) bits and 64 columns is needed.
According to the variable delay circuit
50
shown in
FIG. 1
, since each switch
32
of each delay circuit unit
22
is controlled by the control data outputted from the table
42
, a large amount of data is stored in the table
42
, which in turn makes the volume of the delay circuit
50
large.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a variable delay circuit which is capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, there is provided a variable delay circuit including a delay circuit unit including a first path of a first delay amount and a second path of a second delay amount, wherein an input signal passes through either one of the paths and is outputted; and a control unit for receiving a delay setting value and selecting one path out of the first and second paths by calculating the delay setting value and an offset delay amount corresponding to the first delay amount of the delay circuit unit.
It is possible to reduce the volume of the variable delay circuit since the variable delay circuit does not need to have a table by selecting the path of the delay circuit unit by calculation of the control unit.
According to the first aspect of the present invention, the second delay amount may be substantially zero (0).
The control unit may select the first path in case the offset delay amount is equal to or smaller than the delay setting value, and the second path in case the offset delay amount is larger than the delay setting value, by comparing the offset delay amount with the delay setting value.
According to another embodiment of the first aspect of the present invention, the variable delay circuit includes a plurality of cascaded delay circuit units each of which has a different first delay amount, the control unit includes a plurality of cascaded subtracting units, wherein offset delay amount corresponding to each delay circuit is inputted to each of said subtracting units, and each of the subtracting units receives the delay setting value, and outputs a value, calculated by subtracting the offset delay amount from the delay setting value as a delay setting value for a subtracting unit of the next stage in case the delay setting value is equal to or larger than the offset delay amount, or outputs the delay setting value as a delay setting value for a subtracting unit of the next stage in case the delay setting value is smaller than the offset delay amount.
The plurality of delay circuit units may be cascaded so that the first delay amount of a stage is smaller than that of the previous stage.
A plurality of offset delay amounts, determined to be corresponding to each of selected paths of the delay circuit units in the upstream, may be set for each of the first delay amounts.
The control unit may calculate by using one offset delay amount corresponding to a combination of selected paths of the delay circuit units in the upstream out of a plurality of offset delay amounts set for each of the first delay amounts.
According to another embodiment of the first aspect of the present invention, the variable delay circuit may include a micro variable delay circuit unit which can produce a variable delay amount, which is equal to or smaller than a predetermined first delay amount out of the first delay amounts, and a table for storing data which control the delay amount of the micro variable delay circuit unit.
The control unit may select a path of the delay circuit unit, refer to the data of the table, control the delay amount of the micro variable delay circuit unit and delay the input signal for a predetermined time.
According to a second aspect of the present invention, there is provided a testing apparatus for testing a semiconductor circuit including: a signal generator for generating test signals; a variable delay circuit for providing the test signals outputted from the signal generator with a predetermined timing; and a determining unit for determining whether or not the semiconductor circuit has passed a test based on outputted signals from the semiconductor circuit, wherein the variable delay circuit includes a delay circuit unit including a first path of a first delay amount and a second path of a second delay amount, wherein an input signal passes through either one of the paths and is outputted; and a control unit for receiving a delay setting value and selecting one path out of the first and second paths by calculating the delay setting value and an offset delay amount corresponding to the first delay amount of the delay circuit unit.
The above summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5204564 (1993-04-01), Ochiai
patent: 5420531 (1995-05-01), Wetlaufer
patent: 6297679 (2001-10-01), Kim
patent: 6473455 (2002-10-01), Kwon
patent: 41 10 340 (1993-11-01), None
patent: 59-5736 (1984-01-01), None
patent: 61-128833 (1986-06-01), None
patent: 1-175408 (1989-07-01), None
patent: 5-191233 (1993-07-01), None
patent: 6-45889 (1994-02-01), None
Translation of International Preliminary Examination Report dated Aug. 26, 2002, 4 pages.
Patent Abstracts of Japan, Publication No. 05191233 A, published on Jul. 30, 1993, 1 page.
Patent Abstracts of Japan, Publication No. 59005736 A, published on Jan. 12, 1984, 1 page.
German Office Action dated May 13, 2003, 3 pages with Translation, 4 pages.
Patent Abstracts of Japan, Publication No. 06-045889, Publication date Feb. 18, 1994, 2 pages.
Patent Abstracts of Japan, Publication No. 01-175408, Publication date Jul. 11, 1989, 2 pages.
Mikami Hiroyuki
Tsuruki Yasutaka
Advantest Corporation
Nguyen Linh M.
Rosenthal & Osha L.L.P.
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