Variable delay circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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327288, H03K 513

Patent

active

058595546

ABSTRACT:
A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

REFERENCES:
patent: 5051630 (1991-09-01), Kogan et al.
patent: 5220216 (1993-06-01), Woo
patent: 5285116 (1994-02-01), Thaik
patent: 5430393 (1995-07-01), Shankar et al.
patent: 5509040 (1996-04-01), Shimada
Lewis et al., IBM Technical Disclosure Bulletin, "Variable Delay Driver Circuit"; vol. 22, No. 4, pp. 1405-1406, Sep. 1979.

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