Variable delay circuit

Details Variable delay circuit Variable delay circuit

1995-10-05

1997-11-11

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327285, 327219, 327374, H03K 329, H03K 1716

Patent

active

056868510

ABSTRACT:
A variable delay circuit capable of changing delay time includes a latch circuit constituted of a pair of inverters cross-coupled to each other and a transistor serving for reducing voltage difference between two inputs of the latch circuit based on a control signal given thereto. The control signal is also supplied to a pair of transfer gates to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor is coupled, coupled to the respective transfer gates' ends, at which buffers are respectively coupled to feed output signals. When the control signal reaches a high level, the state of the transistor becomes one of low impedance, so that the voltage difference between the two inputs of the latch circuit is reduced, and so that the state of the latch circuit can be quickly and easily changed with little energy. The variable delay circuit can set the minimum delay time smaller than that of the conventional circuit, which allows the variable range of delay time to be wider.

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K. Tanaka et al, "A GaAs DCFL Variable Delay Circuit for 2.5 GHz" paper presented at the 1991 Spring meeting of the Institute of Electronics, Information and Communication Engineers of Japan (Mar. 1991), p. 5-106.

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