Variable delay circuit

Details Variable delay circuit Variable delay circuit

1995-11-01

1998-01-13

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327291, 327299, 327142, 331 57, 331172, H03L 7099, H03K 513

Patent

active

057083819

ABSTRACT:
In a variable delay circuit including a high-speed clock generator receiving a trigger signal and outputting a pulse signal after a desired time interval upon rising of the trigger signal and a coarse delay signal generator, the high-speed clock generator includes a rising edge detector receiving the trigger signal, detecting a rising edge of the trigger signal, and outputting an edge detecting pulse having a time interval, and an asynchronous reset oscillator receiving the edge detecting pulse, being reset upon rising of the edge detecting pulse, and generating a high-speed clock upon falling of the edge detecting pulse. The high-speed clock generator of the variable delay circuit is realized without using analog circuits. Further, since the high-speed clock generator includes no PLL, it is not necessary to provide analog circuits, such as charge pump and VCO, in a digital LSI and, therefore, special considerations for the analog circuits are eliminated.

REFERENCES:
patent: 4686489 (1987-08-01), Caspell
patent: 5036221 (1991-07-01), Brucculeri et al.
patent: 5175453 (1992-12-01), Chang et al.
patent: 5315166 (1994-05-01), Arimoto
patent: 5315271 (1994-05-01), Pascual et al.
patent: 5355027 (1994-10-01), Shimada et al.
Excerpt from Brooktree catalogue, 1991, pp. 3-2-3-5.

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