Variable delay circuit

Details Variable delay circuit Variable delay circuit

2001-01-30

2003-04-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000

Reexamination Certificate

active

06549052

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a variable delay circuit, which generates a delay amount. In particular, this invention relates to a variable delay circuit, which has a plurality of variable delay elements and generates a desired delay amount. Moreover, this invention relates to a Japanese patent application shown below. For the designated state that permits the incorporation of the literature by reference, the contents mentioned in the application shown below are incorporated into the present application to be a part of the contents of the present application.
Japanese patent application H11-193774, filed on Jul. 7th, 1999.
CONVENTIONAL ART
FIG. 1
shows a block diagram of the conventional variable delay circuit
100
. The variable delay circuit
100
comprises a micro-variable delay unit
12
and a variable delay unit
14
. The micro-variable delay unit
12
has micro-variable delay elements (
12
a-
12
n
). The variable delay unit
14
has a delay unit (
14
a-
14
n
). The micro-variable delay elements
12
generate the delay amount, which is smaller than the delay amount generated by the delay unit (
14
a-
14
n
). Each of the delay units (
14
a-
14
n
) has a different number of gate circuits
11
and generates a delay amount according to the number of gate circuits
11
.
According to the desired delay amount, a delay data, which designates any one of a combination of the micro-variable delay elements (
12
a-
12
n
) and the delay units (
14
a-
14
n
), is provided. An input signal is input and is delayed by the delay element selected by the delay data, and a delay signal is output.
FIG.
2
(
a
) is a circuit diagram that shows a drive-impedance-control-type micro-variable delay element
12
. In a case where a control signal has a truth value of “0”, a drive impedance is set to low. In a case where a control signal has a truth value of “1”, a drive impedance is set to high. Therefore, in a case where the control signal has a truth-value of “1”, the input signal has a delayed output which is a few more than the case of when the truth value is “0”.
FIG.
2
(
b
) is a circuit diagram of a load-capacity-variable-type of micro-variable delay element
12
In a case where a control signal has a truth value of “0”, a load capacity is not set, and in a case where a control signal has a truth value of “1”, the load capacity is set. Therefore, in a case where the control signal has a truth value of “1”, the input signal has a delayed output which is a few more than the case of when the truth value is “0”. The variable delay circuit
100
shown in
FIG. 1
has a micro-variable delay element
12
shown in FIG.
2
(
a
) and FIG.
2
(
b
) and generates a delay amount in a degree from 10 ps to 100 ps for one micro-variable delay element
12
.
FIG. 3
shows a graph for showing the relationship between the delay data, which designates the combination of the delay elements according to the design for generating the desired delay amount, and the delay amount, which is actually generated by the combination of the delay elements set by the delay data. A line “a” shows a straight line, which shows an ideal delay characteristic. In comparison to this, the line “b” generates a delay amount larger than the ideal delay amount. The line “c” generates the delay amount smaller than the ideal delay amount.
Furthermore, the line “b” and the line “c” have a discontinuous part. This is because there are a plurality of different types of the variable delay elements existing in the variable delay circuit
100
, and also because the unevenness of the element characteristics and the influence of the change of the ambient temperature do not necessarily match for each type of the variable delay elements.
There is a case that an error is caused on the delay amount, which is generated by the variable delay circuit
100
between the delay amount actually generated by the delay elements and the delay amount according to the design, by such as the unevenness of the element characteristics of the delay elements, a fluctuation of the self-generated heat quantity of the delay element, a fluctuation of the ambient temperature, and a fluctuation of a power supply voltage.
Therefore, it is an object of the present invention to provide a variable delay circuit that can overcome the above issues. This object is achieved by combinations of characteristics described in the independent claims in the scope of the claim of the invention. The dependent claims define further advantageous embodiments of the present invention.
DISCLOSURE OF THE INVENTION
To solve the above object, the first embodiment of the present invention is a variable delay circuit for generating a desired delay amount comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements included in each of the plurality of referential delay elements, according to a number of the first variable delay elements included in each of the plurality of referential delay units; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.
The referential delay unit may include: a first referential delay unit which has M numbers (M is a natural number) of the variable delay elements; a second referential delay unit that has N numbers (N is a natural number) of the first variable delay elements, the numbers of which are different to the numbers of the first variable delay elements included in the first referential delay unit; the delay compensation unit may have: a first delay compensation unit that generates the control signal provided to the first variable delay elements included in the first referential delay unit; and a second delay compensation unit that generates the control signal provided to the first variable delay element included in the second referential delay unit.
The referential delay unit may have a ring oscillator that has different numbers of the first variable delay elements and generates a predetermined period of an oscillation clock according to the numbers of the first variable delay elements.
The delay compensation unit may further have: a phase comparator that compares a phase of a referential clock having a predetermined period with a phase of a delay clock, which is obtained by delaying the referential clock by the first variable delay elements; and a control signal generating unit which generates the control signal based on the comparison.
The control signal generating unit may generate the control signal so that a phase of the referential clock and phase of the delay clock matches.
The variable delay circuit may further comprise a selector that provides any one of a plurality of the control signals provided from the delay compensation unit to the second variable delay elements.
The first variable delay element may have a capacitor that has a predetermined capacitance and a time constant control unit for changing a time constant of the capacitor and may change a delay amount according to the time constant.
The time constant control unit may have a transistor and may change a time constant of the capacitor by changing a gate voltage applied to the transistor.
The second embodiment of the present invention is a variable delay circuit which generates a desired delay amount for a signal to be output to an output terminal that comprises: a variable delay element that has a capacitor having a predetermined capacitance and a time constant control unit, which is serially inserted between the capacitor and the output terminal for changing a time constant of the capacitor, and changes a delay amount according to the time constant; and a delay unit which generates the desired delay amount by selecting th

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