Variable delay circuit

Details Variable delay circuit Variable delay circuit

1999-10-27

2001-11-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S263000, C327S291000, C327S161000, C327S176000

Reexamination Certificate

active

06313681

ABSTRACT:

BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable delay circuit suitable for an LSI tester, and more particularly to a variable delay circuit improved in speed and accuracy.
2. Description of the Related Art
Recently, with the speed-up of semiconductor integrated circuits, there arises a demand for a more accurate LSI tester and there is an increase in the frequency to be dealt with. The performance of an LSI tester depends on the performance of a variable delay circuit integrated therewith.
FIG. 18
is a circuit diagram showing a conventional variable delay circuit. The conventional variable delay circuit is provided with two delay circuits DLY
101
and DLY
102
having the same structure. The delay circuit DLY
101
comprises a ramp generator RG
51
, a comparator CP
51
connected to the ramp generator RG
51
, an inverter IV
51
connected to the comparator CP
51
, and a capacitive element C
51
connected between the ramp generator RG
51
and the comparator CP
51
.
The delay circuit DLY
102
also comprises a ramp generator RG
52
, a comparator CP
52
, an inverter IV
52
, and a capacitive element C
52
. A signal line at the analog-output potential ANG
51
is connected to the comparator CP
51
and the comparator CP
52
. The ramp generator RG
51
is connected to an input terminal DI
51
, the inverter IV
52
is connected to an output terminal DO
51
, and the inverter IV
51
is connected to the ramp generator RG
52
.
In the conventional variable delay circuit thus constituted, the delay circuit DLY
101
of the first step delays the H→L edge of an input signal through the input terminal DI
51
and the logic thereof is inverted by the inverter IV
51
. Next, the delay circuit DLY
102
of the second step delays the H→L edge of the inverted signal, thereby delaying the L→H edge of the input signal through the input terminal DI
51
in fact, and the logic thereof is inverted by the inverter IV
52
. The signal in which the H→L edge and L→H edge is delayed is supplied to the output terminal DO
51
. Generally, a delay circuit can only delay the H→L edge, which makes a signal inverted twice by the inverter IV
51
and IV
52
as mentioned above.
It is necessary to establish the analog-output potential ANG
51
between the Lo level and Hi level output from the ramp generators RG
51
and RG
52
, so as to invert the logic completely, with some margin enough to prevent from malfunction due to a noise. A delay setting signal is usually entered in digital form, and this digital signal is converted into an analog signal by a digital-to-analog converter (DAC: Digital-Analog Converter). In this case, since the analog signal will be varied accordingly to the change even if there is a change in the manufacturing process or power voltage, it is not necessary to consider any margin and the signal can be handled easily.
The conventional variable delay circuit, however, imposes a great restriction on the operating frequency in case of needing to achieve a high accuracy. This is why the proximity of L→H edge and H→L edge owing to the speed-up disturbs assurance of accuracy because the delay time is deviated by the effect of an overshoot.
FIG. 19
is a timing chart showing a signal transferred within the conventional variable delay circuit.
FIG. 20
is a graph showing the relationship therebetween with the analog output setting potential fixed as a horizontal axis and the delay time fixed as a vertical axis; FIG.
20
(
a
) shows the H→L edge, and FIG.
20
(
b
) shows the L→H edge.
FIG. 21
is a graph showing the relationship therebetween with the analog output setting potential fixed as a horizontal axis and the duty ratio fixed as a vertical axis. In FIGS.
20
(
a
) and (
b
) and
FIG. 17
, the analog output potential is lower at the right side.
In the above-mentioned conventional variable delay circuit, when the ramp generator RG
51
receives L→H edge of a signal input through the input terminal DI
51
, the capacitive element C
51
is immediately charged, with no generation of delay (node N
51
). The L→H edge is entered into the comparator CP
51
, L→H change occurs at the output side of the comparator CP
51
(node N
52
). The edge is logically inverted by the inverter IV
51
and the potential of the signal changes from H to L (node N
53
).
While, when the ramp generator RG
51
receives H→L edge of a signal input through the input terminal DI
51
, the electric charge Q filled with the capacitive element C
51
is gradually released by the constant-current power supply within the ramp generator RG
51
, thereby making a ramp waveform such as the potential gradually lowers (node N
51
). When the ramp waveform lowering at a constant gradient reaches the same potential as the analog output potential ANG
51
, the logic of the output of the comparator CP
51
is inverted from H to L (node
52
). Further, the edge is logically inverted by the inverter IV
51
and the logic of the signal changes from L to H (node N
53
).
When the repeated waveform of L→H edge and H→L edge is entered into the input terminal DI
51
and the signal output from the inverter IV
51
is supplied to the delay circuit DLY
102
, the H→L edge is entered in the ramp generator RG
52
during disturbance of the waveform at the L→H edge due to an overshoot. Therefore, discharge from the capacitive element C
52
when the H→L linear waveform is entered in the ramp generator RG
52
is started from the higher potential position or from the lower potential position than in the case where no overshoot occurs. Namely, the H→L linear waveform makes such a shape as moving in parallel vertically from the position where no overshoot occurs. Thus, the time when the H→L linear waveform reaches the same potential as the analog potential ANG
51
is varied, thereby causing a change in the delay time as illustrated in FIGS.
20
(
a
) and (
b
) and deteriorating the accuracy.
Since it is only at one edge that the delay time is varied by an overshoot, the duty ratio is varied according to the setting potential, as illustrated in FIG.
21
. The L/H ratio of the output waveform of the delay circuit DLY
101
is also varied according to the setting potential, thereby changing the influence of the overshoot in the delay circuit DLY
102
. This is the cause of deteriorating the linearity. It is a problem that the quality will be destroyed in order to speed up the performance.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a variable delay circuit capable of preventing from deterioration of the duty ratio and the linearity in an output signal even if there occurs some edge whose delay time is deviated by an overshoot within a circuit, thereby setting the delay time at a high accuracy even if speeding up the performance.
According to one aspect of the invention, a variable delay circuit comprises
an input terminal,
a positive logic variable delay circuit for delaying an edge of a signal input through the input terminal,
a negative logic variable delay circuit for delaying an edge of a signal input through the input terminal, and
an extracting circuit for extracting only the edge delayed in accordance with set time from the edges of a signal supplied from the positive logic variable delay circuit and the edges of a signal supplied from the negative logic variable delay circuit.
According to the present invention, the edge of a signal input through the input terminal is delayed by a variable delay circuit of positive logic as well as delayed by a variable delay circuit of negative logic. From the edges supplied therefrom, only the edge delayed just according to the set time is extracted by an extracting circuit. Therefore, a delay circuit according to the present invention doesn't supply any edge whose delay time has been deviated due to an overshoot, thereby assuring a high accuracy even if speeding up.
In the preferred construction, the positive logic variable delay circuit includes delay time incre

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