Variable delay circuit

Details Variable delay circuit Variable delay circuit

1998-01-29

2001-10-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S276000, C327S288000

Reexamination Certificate

active

06304124

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a variable delay circuit and, more particularly, to a variable delay circuit for providing a variable delay time capable of being controlled by a set of control signals.
(b) Description of the Related Art
A variety of variable delay circuits have been proposed each providing a variable delay time capable of being controlled by a set of control signals supplied from outside the circuit. Since the variable delay circuit can be designed to implement a voltage controlled oscillator by connecting the output of the variable delay circuit with the input thereof for a negative feedback loop, it is sometimes described as a programmable voltage controlled oscillator.
U.S. Pat. No. 4,978,927 to Hausman et al. discloses a programmable voltage controlled oscillator shown in FIG.
1
. The voltage controlled oscillator has three basic gate circuits
202
,
204
and
206
, a first gate circuit
232
and a second gate circuit
226
, all of which are connected to form a ring oscillator, with one of two signal paths in each of the basic gate circuits
202
,
204
and
206
being selected by selecting a set of control signals “A”, “B” and “C” to selectively short-cutting a signal path portion of the ring oscillator. By this configuration, the voltage controlled oscillator achieves a variable oscillator frequency.
Patent Publication JP-A-5(1993)-268002 proposes another voltage controlled oscillator shown in
FIG. 2
, wherein a NAND gate
305
including an associated transistor N
52
and a plurality of inverters
301
to
304
each including an associated transistor N
12
, N
22
, n
32
or N
42
are cascaded, with the output of the last stage inverter
304
being fed-back to the first input of the NAND gate
305
. The current of each of the NAND gate
305
and inverters
301
to
304
is controlled by the associated transistors receiving an analog control signal “IN” for controlling the ON-resistance of the associated transistors, thereby obtaining a variable delay time in the voltage controlled oscillator. The NAND gate
305
also receives a control signal CR through the second input thereof for starting or stopping the oscillation. In this configuration, a wide range of oscillator frequency can be obtained.
In the conventional voltage controlled oscillators as mentioned above, there is a problem in that the gains of the voltage controlled oscillators of the same design differ from each other due to the variation caused by a fabrication process or the gain of a voltage controlled oscillator changes with the change of the operational temperature. This is common to a digital circuit and an analog circuit. The term “gain” as used herein means the ratio of the amount of the change in the resultant delay time to the amount of the change in the control signal (set of control signals), which may be expressed in terms of either analog or digital magnitude, supplied to the voltage controlled oscillator which is operating to provide a desired delay. For example, the delay of a typical basic gate formed by transistors generally ranges between about 0.5 times and 2.0 times normal delay, which involves the gain of the voltage controlled oscillator ranging between 0.5 and 2.0.
In addition, in the voltage controlled oscillator disclosed in U.S. Pat. No. 4,978,927, the delay can be controlled stepwise specified by a unit time corresponding to the delay of each basic gate circuit. Accordingly, a finer adjustment cannot be obtained. This is peculiar to the case of the digital circuit. For example, the delay of a basic gate is about 100 pico-second (ps) in the case of 0.2 &mgr;m CMOS-LSI ata source voltage of 2.5 volts, which limits the unit delay to 100 ps.
In the case of the voltage controlled oscillator described in JP-A-5-268002, since the control range is limited by a source voltage, a higher gain causes the oscillator to be more susceptible to noise. This is peculiar to the case of an analog circuit. Specifically, the control range of an analog control signal generally depends on the source voltage. Accordingly, if a wide range of the delay is desired for the voltage controlled circuit, it is generally achieved by a large gain of the voltage controlled oscillator, which causes that only small noise in the control signal generates large noise in the output delay.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a new variable delay circuit.
It is an additional object of the present invention to provide a variable delay circuit capable of providing a high accuracy of the gain irrespective of the variations in the device characteristics caused by the fabrication steps or the operational temperature or less susceptible to noise in the control signal.
The present invention provides, in a first aspect thereof, a variable delay circuit comprising a gate element for receiving a first signal to output a second signal corresponding to the first signal through an output line, and a plurality of (N) delay elements each having a control input f or receiving a corresponding one of a set of N control signals to delay a signal change of the second signal, wherein a difference between a first delay provided by an n-th delay element and a second delay provided by an (n+1) th delay element is substantially constant for any of n's between 1 and N−1.
The present invention also provides, in a second aspect thereof, a variable delay circuit comprising a plurality of cascaded variable sections each having: a gate element for receiving a first signal to output a second signal corresponding to the first signal; and a plurality of (N) delay elements each having a control input f or receiving a corresponding one of a set of N control signals to delay a signal change of the second signal.
In accordance with the variable delay circuit of the preferred embodiment, a wide range for the delay can be obtained in a single variable delay circuit with a fine control of delay.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 4458165 (1984-07-01), Jackson
patent: 5039893 (1991-08-01), Tomisawa
patent: 5111085 (1992-05-01), Stewart
patent: 5121014 (1992-06-01), Huang
patent: 5440260 (1995-08-01), Hayashi et al.
patent: 5708396 (1998-01-01), Mizuno
patent: 5859554 (1999-01-01), Higashisaka et al.
patent: 5898321 (1999-04-01), nkbahar et al.
patent: 5917758 (1999-06-01), Keeth
patent: 53057731 (1978-05-01), None
patent: 61-224616 (1986-10-01), None
patent: 62274913 (1987-11-01), None
patent: 4978927 (1990-12-01), None
patent: 5-136664 (1993-06-01), None
patent: 5268002 (1993-10-01), None
patent: 7-170162 (1995-07-01), None
patent: 7202646 (1995-08-01), None
patent: 8-102643 (1996-04-01), None

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