Variable delay circuit

Details Variable delay circuit Variable delay circuit

1998-09-03

2001-01-02

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S269000

Utility Patent

active

06169436

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority of the prior French Patent Application No. 97-11022, filed Sep. 4, 1997, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to variable delay circuits, and more specifically to variable delay circuits whose delay can be adjusted as a function of a delay instruction, which can take the form of a numerical variable.
2. Description of Related Art
The applications of variable delay circuits are numerous. For example, delay circuits are used for phase adjustments between two logic signals. In particular, one signal is supplied to the input of a delay circuit and the delay of the delay circuit is then adjusted using the measurement of the phase shift between the two logic signals. A phase locked loop circuit is controlled on the basis of an analog or digital setting signal. The digital approach is generally preferred because it is less sensitive to disturbances and to attenuation due to signal transmission. Furthermore, in integrated circuit form, the digital approach is less sensitive to manufacturing variations.
A first conventional digitally-controlled delay circuit uses a set of elementary gates such as inverters. All of the gates are associated with a digitally-controlled interconnection system that enables a cascade connection of a variable number of the elementary gates. This type of circuit is limited to applications in which it is not necessary to obtain greater precision in setting the delay than the intrinsic delay of an elementary gate.
Another conventional delay circuit uses a resistor/capacitor-type circuit in which the resistor consists of several elementary resistors that are connected together in parallel as a function of the digital command. The delay is fixed by the time constant of the circuit so if all of the elementary resistors have the same value, the delay is inversely proportional to the number of resistors selected. To obtain a delay precision that is constant throughout the setting range, it is necessary for the function linking the delay to the numerical setting variable to approach a linear function. However, the response obtained by the resistor/capacitor-type circuit is far from such a linear relationship, and is actually of a hyperbolic type. To approach the linear response, it is necessary to size the elementary resistors at values that are quite precise and different from one another. However, such exact circuit elements are very difficult to obtain in integrated circuit form. Furthermore, it is necessary to provide such a circuit for each signal whose phase is to be adjusted.
If the delay circuit is to be used in a phase locked loop circuit of the type described in European Patent Application (published) No. 0 441 684, filed Jan. 30, 1991, for “Circuit verrouille en phase et multiplieur de frequence en resultant” (Phase Locked Circuit and Frequency Multiplier Resulting Therefrom), the above approach is not satisfactory because of the required size and the sensitivity to manufacturing variations. While the variable delay circuit of French Patent No. 2 690 022, for “Circuit {grave over (a)} retard variable” (Variable Delay Circuit) provides a linear response for the delay as a function of the delay instruction, the amplitude of the delay range is not technologically satisfactory. To overcome this problem, the circuit of French Patent No. 2 689 339, for “Proc{acute over (e)}d{acute over (e)} et dispositif de reglage de retard {grave over (a)} plusieurs gammes” (Method and Device for the Setting of Delay with Several Ranges) employs the concept of multiple ranges. However, in practice, problems of linearity of the delay as a function of the delay instruction are encountered.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a delay circuit that enables a precise delay setting and at the same time ensures, with sufficient approximation, a linear response of the delay as a function of the delay instruction during a substantial time interval in order to approach a constant setting precision.
Another object of the present invention is to provide a delay circuit having an output signal that is delayed with respect to an input signal, with the delay being adjustable as a function of a delay instruction. The delay circuit has a primary circuit, a combination circuit, and a shaping circuit. The primary circuit receives the input signal and generates two intermediate signals having a fixed delay therebetween. The combination circuit has a control input that receives a control variable representing the delay instruction, and two signal inputs that receive the intermediate signals. The combination circuit outputs a combination signal that results from a superimposition, with a weighting and integration effect, of the intermediate signals. In a preferred embodiment, each of the input signals is weighted by a weighting coefficient, with the values of the weighting coefficients being a function of the control variable.
The combination signal from the combination circuit is input to the shaping circuit. The shaping circuit, which has a threshold effect, produces an activation signal when the combination signal (by integration effect) reaches a specified threshold. Thus, the effective delay of the output signal with respect to the input signal depends on the level of the combination signal. It is desirable that the maximum and minimum amplitudes of the combination signal should be independent of the delay instruction, so the sum of the two weighting coefficients is constant. In the preferred embodiment, the integration is produced by an integrator or a time constant circuit that has a saturation effect defining the extreme levels of the combination signal.
During operation, the transition time is defined as the interval during which the combination signal varies according to a linear or quasi-linear function when one of the weighting coefficients associated with the intermediate signals is zero. By dictating a fixed delay smaller than the transition time, the delay of the output signal with respect to the input signal does not have any discontinuity as a function of the weighting coefficients. In order for the delay variation (as a function of the delay instruction) to vary throughout the setting range according to a substantially linear function of the instructed value, the combination circuit and/or the primary circuit can be sized so that the fixed delay will be equal to half of the transition time.
This constraint linking the fixed delay and the transition time prevents the widening of the amplitude of the delay range in the circuit of French Patent No. 2 690 022 (see above). The delay range is defined by the fixed delay circuit. If this fixed delay is increased, there is no longer the condition of a fixed delay that is equal to half the transition time. This condition is necessary to ensure the linearity of the delay of the output signal in relation to the input instruction. To overcome this problem, French Patent No. 2 689 339 provides a modified primary circuit. A set of cascade-connected delay circuits is used, and the outputs of these cascade-connected delay circuits are connected to a multiplexer. The multiplexer is used for the selection (by way of intermediate signals) of pairs of signals possessing a fixed delay (as before) and a basic delay with respect to the input signal. When the range is being changed, technological delay gaps or discontinuities are observed. If the discontinuity is negative, it becomes impossible for the servo-control arrangement to find a balanced setting at an acceptable value. In the present invention, this problem is overcome by modifying the combination circuit so as to enable a full range to be used.
Yet another object of the present invention is to provide a delay circuit that is specially designed for fabrication using CMO

Affiliated with

Also associated with

Rating

Variable delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2444068