Variable delay cell with hysteresis and ring oscillator using sa

Details Variable delay cell with hysteresis and ring oscillator using sa Variable delay cell with hysteresis and ring oscillator using sa

1997-06-13

1999-09-14

Grimm, Siegfried H.

Oscillators

Ring oscillators

327264, 327281, H03B 502

Patent

active

059528915

ABSTRACT:
A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term "hysteresis" as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.

REFERENCES:
patent: 5208557 (1993-05-01), Kersh, III
patent: 5250914 (1993-10-01), Kondo
patent: 5459437 (1995-10-01), Campbell
patent: 5621360 (1997-04-01), Huang
Sarbacher, Encyclopedic Dictionary of Electronics and Nuclear Engineering, p. 608, Prentice-Hall, Inc. 1959.
IEEE Journal of Solid State Circuits, vol. 22, No. 2, Apr. 1, 1987, New York, U.S., pp. 255-261, XP002027247 D. Jeong: "Design of PLL Based Clock Generation Circuits".

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