Variable delay cell with a self-biasing load

Details Variable delay cell with a self-biasing load Variable delay cell with a self-biasing load

1998-01-14

1999-11-30

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327287, 327 65, 327563, 330257, H03K 513, H03K 1728

Patent

active

059949392

ABSTRACT:
A variable delay cell with a self-biasing load suitable for the implementation of a voltage controlled oscillator and other functions. Because the invention employs current steering between symmetric loads and fully differential voltage control, it is very fast relative to conventional methods and has reduced jitter and improved power supply noise rejection. Additionally, since the load is self-biasing, the need to externally generate a bias current for the load is eliminated. This significantly simplifies design. Also as the load readily self biases in response to changes in the bias current of the biasing transistor, desirable functionalities can be achieved merely by appropriately changing the bias current into the biasing transistor. Notably, the slew rate of both the rising and falling edge can be controlled in this way. Because the load provides a fully differential output, noise immunity as well as a 50% duty cycle is readily achieved.

REFERENCES:
patent: 4866314 (1989-09-01), Traa
patent: 5422529 (1995-06-01), Lee
patent: 5546052 (1996-08-01), Austin et al.
patent: 5576647 (1996-11-01), Sutardja et al.
"Comparator with Hysteresis," Allen, Phillip E., and Holberg, Douglas R., CMOS Analog Circuit Design, 1987, pp. 349-352.

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