Variable delay buffer circuit

Details Variable delay buffer circuit Variable delay buffer circuit

1994-06-23

1995-11-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327153, 327161, H03K 513, H03L 700

Patent

active

054670411

ABSTRACT:
A variable delay buffer circuit composed of a cascade of variable delay buffers, which realizes a delay in response to a delay control signal without any glitches. The delay buffers each have a selector circuit for selecting one of an input signal and a delayed signal produced by delaying in time the input signal in response to a delaying information. The delay buffers each contains a first control means and an output means. The first control means controls a timing of a input of the delaying information into the selector circuit in response to an external control signal. The output means outputs the control signal to by synchronized with an output signal from the selector circuit. Preferably, the first control means contains a latching means for latching the delay information and a second control means for controlling a timing in output of the delay information from the latching means in response to the control signal.

REFERENCES:
patent: 4458165 (1984-07-01), Jackson
patent: 4737670 (1988-04-01), Chan
patent: 5103185 (1992-04-01), Arai
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5327031 (1994-07-01), Marbot et al.

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