Variable delay branch system

Details Variable delay branch system Variable delay branch system

1988-08-15

1990-11-27

Heckler, Thomas M.

Boots, shoes, and leggings

3642318, 3642615, G06F 942

Patent

active

049741551

ABSTRACT:
In a pipeline computer, current instructions executed in sequence are monitored for conditional and unconditional branch commands, as well as the readiness of condition codes, the meeting of branch conditions and split commands. A branch command initiates an interval of delay which affords prefetching target instructions while using pipeline contents to prevent a pipeline break and avoid lost time. Detection of a branch command actuates a register to store a sequence of target instructions. Unless a branch command is conditional, subsequent detection (delayed) of a split command shifts the stored target instructions into operation as the current instructions. For a conditional branch command, a jump or split to the target instructions is performed only if the condition is met. Otherwise the current instruction sequence is restored pending another branch command. Dual instruction registers, program counters and address registers alternate to accommodate branch jumps with considerable time savings by effective programming.

REFERENCES:
patent: 4338661 (1982-07-01), Tredennick et al.
patent: 4435756 (1984-03-01), Potash
patent: 4471433 (1984-09-01), Matsumoto et al.
patent: 4498136 (1985-02-01), Sproul, III
patent: 4546431 (1985-10-01), Horvath
patent: 4656578 (1987-04-01), Chilinski et al.

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