Variable decimation architecture for a delta-sigma analog-to-dig

Details Variable decimation architecture for a delta-sigma analog-to-dig Variable decimation architecture for a delta-sigma analog-to-dig

1991-03-04

1992-10-20

Logan, Sharon D.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

3647241, H03M 732, G06F 1531

Patent

active

051573954

ABSTRACT:
An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.

REFERENCES:
patent: 4588979 (1986-05-01), Adams
patent: 4746899 (1988-05-01), Swanson et al.
patent: 4851841 (1989-07-01), Sooch
patent: 4999626 (1991-03-01), Asghar et al.
patent: 5012245 (1991-04-01), Scott et al.
patent: 5051981 (1991-09-01), Kline
Friedman et al., "A Dual-Channel Voice-Band PCM Codec Using .SIGMA..DELTA. Modulation Technique", IEEE Journal of Solid State Circuits, vol. 24, No. 2, Apr. 1989.
Friedman et al., "A Bit-Slice Architecture for Sigma-Delta Analog-To-Digital Converters", IEEE Journal of Solid State Circuits, 1988.

Affiliated with

Also associated with

Rating

Variable decimation architecture for a delta-sigma analog-to-dig does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable decimation architecture for a delta-sigma analog-to-dig, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable decimation architecture for a delta-sigma analog-to-dig will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-195152