Boots – shoes – and leggings
Patent
1993-08-26
1995-08-29
Eng, David Y.
Boots, shoes, and leggings
36424341, 36424343, 3649642, G06F 1212, G06F 1300
Patent
active
054468612
ABSTRACT:
An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.
REFERENCES:
patent: 3422401 (1969-01-01), Lucking
patent: 3569938 (1971-03-01), Edea et al.
patent: 3647348 (1972-03-01), Smith et al.
patent: 3737881 (1973-06-01), Cordi et al.
patent: 3761883 (1973-09-01), Alvarez et al.
patent: 3898626 (1975-08-01), Hutson
patent: 3949369 (1976-04-01), Churchill
patent: 3967247 (1976-06-01), Anderson
patent: 4020466 (1977-04-01), Cordi et al.
patent: 4032899 (1977-06-01), Jenny
patent: 4038642 (1977-07-01), Boulenecht
patent: 4042972 (1977-08-01), Gruner
patent: 4062059 (1977-12-01), Suzuki
patent: 4070706 (1978-01-01), Scheuneman
patent: 4073005 (1978-02-01), Parkin
patent: 4073005 (1978-02-01), Parkin
patent: 4075686 (1978-02-01), Calle et al.
patent: 4075691 (1978-02-01), Davis
patent: 4078254 (1978-03-01), Beausoleil et al.
patent: 4084231 (1978-04-01), Capozzi et al.
patent: 4133030 (1979-01-01), Huettner
patent: 4179737 (1979-12-01), Kim
patent: 4186438 (1980-01-01), Benson et al.
patent: 4215400 (1980-07-01), Denko
patent: 4236210 (1980-11-01), Terakawa
patent: 4394732 (1983-07-01), Swenson
patent: 4394733 (1983-07-01), Swenson
patent: 4399503 (1983-08-01), Hawley
patent: 4413317 (1983-11-01), Swenson
patent: 4415970 (1983-11-01), Swenson et al.
patent: 4419725 (1983-12-01), George et al.
patent: 4423479 (1983-12-01), Hansen et al.
patent: 4425615 (1984-01-01), Swenson et al.
patent: 4433374 (1984-02-01), Hansen et al.
patent: 4437155 (1984-03-01), Sawyer et al.
patent: 4506323 (1985-03-01), Pusic et al.
patent: 4523206 (1985-06-01), Sasseer
patent: 4523275 (1985-06-01), Swenson et al.
patent: 4530054 (1985-07-01), Hamstra et al.
patent: 4530055 (1985-07-01), Hamstra et al.
patent: 4598357 (1986-07-01), Swenson et al.
patent: 4811203 (1989-03-01), Hamstra
patent: 4868734 (1989-09-01), Idelman et al.
patent: 5241666 (1993-08-01), Idelman et al.
PDP 11/70 Processor Handbook, Digital Equipment Corporation, 1976, start to pp. iv, pp. 1-1, 6-10, 6-11, 6-16 to 6-17.
A. J. Smith, "An Analytic and Experimental Study of Multiple Channel Controllers", IEEE Transactions On Computers, vol. C-27, No. 1, Jan. 1979 pp. 38-49.
VAX-11 Software Handbook, Digital Equipment Corporation, 1978, start to pp. vii, pp. 119, 133-135, 152-156, 180-185, 388-389.
Memorex, 3770 Disc Cache Product Description Manual, Memorex Corporation, Santa Clara, California.
Y. Chu, Editor, High-Level Language Computer Architecture, Academic Press, New York, San Francisco, London, 1975.
G. D. Chesley and W. R. Smith, "The Hardware-Implemented High-Level Machine Language for SYMBOL" AFIPS Conference Proceedings, 1971, Spring Joint Computer Conference, vol. 38, pp. 563-616, May 18-20, 1971, Atlantic City, New Jersey.
A. J. Smith, Univ. of California, Berkeley, Calif., "On Effectiveness of Buffered and Multiple Arm Disks", Proc. 5'th ISCA, pp. 242-248, Apr. 1978.
A. J. Smith, Univ. of California, Berkeley, Calif., "Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through", Journal of the Association for Computing Machinery,vol. 26, No. 1, Jan. 1979, pp. 6-27.
D. N. Freeman and J. R. Ragland, "The Response-Effiency Trade-Off in a Multiple-University System", Datamation, Mar. 1970, vol. 16, No. 3, pp. 7, 112-113 and 116.
D. N. Freeman, "A Storage-Hierarchy System for Batch Processing", Proc. STCC, 1968, pp. 229-243, 1968.
D. A. Stevenson and W. H. Vermillion, "Core Storage as a Slave Memory for Disk Storage Devices", Information Processing 68, pp. 1277-1284, North-Holland Pub. Co., Amsterdam 1969.
T. Welch, "Effects of Sequential Data Access on Memory Hierarchy Design", IEEE Computer, 1979, pp. 65-68.
T. Welch, "Analysis of Memory Hierarchies for Sequential Data Access", IEEE Computer, May 1979, pp. 19-26.
IBM Technical Disclosure Bulletin, vol. 19, #2, Jul. 1976, pp. 597-598.
Article, "Memorex Maximizes Disc Drive Performance with Microprocessor-Controlled CCDs", Memorex News, Apr. 25, 1978.
Idleman Thomas E.
Stamness Jesse I.
Cass Nathan
Eng David Y.
Starr Mark T.
Unisys Corporation
LandOfFree
Variable data rate improvement of disc cache subsystem does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable data rate improvement of disc cache subsystem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable data rate improvement of disc cache subsystem will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1826836