Variable clocking in hardware co-simulation

Details Variable clocking in hardware co-simulation Variable clocking in hardware co-simulation

2011-05-03

2011-05-03

Proctor, Jason (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

In-circuit emulator

Reexamination Certificate

active

07937259

ABSTRACT:
Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

REFERENCES:
patent: 7085976 (2006-08-01), Shirazi et al.
patent: 7143369 (2006-11-01), Milne
patent: 2003/0171908 (2003-09-01), Schilp et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
“Xplorer: Xplorer maximizes design performance” downloaded from http://www.xilinx.com/products/design—tools/logic—design/implementation/xplorer.htm, Dec. 12, 2007,1 page, Xilinx, Inc. 2100 Logic Drive, San Jose, California.
Hitesh Patel, “Accelerate Design Performance Using Xplorer”, Xcell Journal, Fourth Quarter 2005, Dec. 1, 2005, pp. 25-27.

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