Multiplex communications – Communication over free space – Combining or distributing information via code word channels...
Reexamination Certificate
1999-07-06
2003-12-02
Trost, William (Department: 2738)
Multiplex communications
Communication over free space
Combining or distributing information via code word channels...
C370S441000, C370S442000, C375S213000, C375S213000
Reexamination Certificate
active
06657986
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a correlation circuit, and more particularly, to a variable clock rate correlation circuit for use in a portable CDMA receiver.
Correlation circuits are commonly used in portable telecommunications receivers for identifying which transmission among many signals is intended for the particular receiver. The correlation circuit generates a locally generated signal and compares that local signal to the received signal. When the received signal and the locally generated signal have a high degree of correlation, the transmission is deemed to be intended for the receiver. When the resulting correlation is low, the transmission is deemed not intended for the receiver and discarded. The received and locally generated signals may be either analog signals, such as those used in FM telecommunications systems, or sequences of binary data in digital systems such as Code Division Multiple Access (CDMA) systems.
Correlation circuits are used throughout the receiver, including in the carrier lock loop and delay lock loop circuitry of the receiver. A carrier lock loop (CLL) is used to remove the carrier offset frequency and phase of the received signal. A delay lock loop (DLL) is used to maintain signal lock, i.e., maintain the alignment between the received and locally generated signals once the received signal has been acquired.
FIG. 1A
illustrates a system block diagram of a carrier lock loop (CLL) for a digital CDMA receiver. The CLL includes a complex multiplier
102
, a correlation circuit
103
, an arc-Tangent look up table (ATAN LUT)
104
, a loop filter
105
, and a numerically controlled oscillator (NCO)
106
. Using a CDMA receiver front end (not shown), a CDMA signal is received and downconverted to baseband I and Q data sequences
101
a
and
101
b.
The I and Q data sequences
101
a
and
101
b
are supplied to the complex multiplier
102
with complex multipliers sin(&PHgr;)
106
a
and cos(&PHgr;)
106
b
. The complex multipliers
106
a
and
106
b
operate to remove the carrier frequency and phase offset from the carrier signal. The I and Q data sequences
102
a
and
102
b
are correlated with locally generated sequences (not shown), producing complex phase error components cos(&PHgr;)′
101
a
and sin (&PHgr;)′
103
b
. The complex phase error components
103
a
and
103
b
are supplied to an Arc-tangent look-up table
104
, which produces a phase error signal
105
a
. The phase error signal
104
a
is a measure of how closely aligned the received I and Q data carrier offset phase is to the locally generated phase (&PHgr;). The phase error will be minimum when the received carrier phase and &PHgr; are aligned. A loop filter
105
removes any spurious out-of-band signal components from the phase error signal
103
a
. The phase error signal is supplied to a numerically controlled oscillator (NCO)
106
, which in response produces an improved set of complex multipliers
106
a
and
106
b.
Once the received sequence is matched to the local PN sequence, the alignment between the two sequences must be closely maintained.
FIG. 1B
illustrates a block diagram of a delay lock loop for dynamically maintaining alignment between the received and local PN sequences once the two sequences are within a predefined range. The delay lock loop
100
includes correlators
110
a-c
, filters
120
a-c
, an adder
122
, a loop filter
132
, a voltage controlled oscillator (VCO)
134
, and a local pseudo-normal (P-N) code generator
136
. A received chip sequence
102
is concurrently supplied to correlators
110
a-c
. The PN generator
136
generates a three local PN sequences
104
a-c
. The first local PN sequence
104
a
is punctual with the received PN sequence
102
. The correlator
110
a
produces the response shown in FIG.
1
C.
When the alignment between the received PN sequence and the Local PN sequence are varied from −T to T, the second local PN sequence
104
b
is late with respect to the received PN sequence
102
, thereby generating the output response
125
shown in FIG.
1
D. The third local PN sequence
104
c is early with respect to the received PN sequence
102
generating an output response
125
c
which is shown in FIG.
1
E. The early and late versions of the received and locally generated sequences are typically used in the correlation circuits, as shown below.
An adder
122
is used to sum a negated version of the late response with the early response to generate an error signal
130
, shown in FIG.
1
F. As shown in
FIG. 1F
, the error signal
130
has a linear voltage level versus time response over the correlation period ±T/2. Once the locally generated and received sequences are within this range, the DLL dynamically realigns them until the error signal
130
reaches zero, indicating perfect alignment between the two.
A loop filter
132
removes spurious noise from the error signal
130
which may occur during the correlation process. The filtered error signal is supplied to the VCO
134
, which generates a tone corresponding to the error signal
130
. The local PN generator
136
receives the VCO tone, and in response, adjusts the timing of its internally generated local PN sequences
104
a-c
, either advancing or delaying the local PN sequences
104
a-c
according to error signal response of FIG.
1
F. The adjusted local PN sequences
104
a-c
are then output to the correlators
110
a-c
to obtain a higher degree of correlation with the received PN sequence.
Correlation circuits consume power primarily as a function of its operating speed or correlation rate. A correlation circuit operating at a high clock rate consumes more power than the correlation circuit operating at a lower clock rate.
In conventional receiver circuitry such as the aforementioned CLL and DLL, the correlation rate is maintained at a constant clock rate, typically many times higher than the chip rate of the received signal or sequence. The cumulative effect of a large number of correlation circuits operating at a relatively high clock rate results in a significant consumption of power. In light of the limited power supply available to portable cellular telephones, the present method of operating the correlation circuits become very disadvantageous.
What is needed is a new correlation circuit and method of operation which allows a reduction in the clock rate and accordingly, a decrease in power consumption.
SUMMARY OF THE INVENTION
The present invention provides for a variable clock rate correlation circuit which conserves power by operating at two different clock rates. During initial signal acquisition, the variable clock rate correlation circuit operates at a high clock rate, 2 or more times the chip rate to correlate the received and locally generated sequences for a possible match. Once the received and local generated sequences exhibit a high degree of correlation, the relative positioning of the received and locally generated sequences is known to a large degree. The variable clock rate correlation circuit then switches to a lower clock rate, less than twice the chip rate, reducing the amount of power it consumes, while maintaining a high degree of time alignment accuracy.
In one embodiment, the correlation circuit includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result.
REFERENCES:
patent: 4553251 (1985-11-01), Hartmann
patent: 4558422 (1985-12-01), DenBeste
patent: 4901307 (1990-02-01), Gilhousen
patent: 5268
Kang Inchul
Laudel Kennan
Hyundai Electronics America
Miller Brandon J.
Trost William
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