Variable clock rate analog-to-digital converter

Details Variable clock rate analog-to-digital converter Variable clock rate analog-to-digital converter

2006-08-08

2006-08-08

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C327S158000, C713S500000

Reexamination Certificate

active

07088275

ABSTRACT:
An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream. The internal clock, in turn, has a variable period allocating more time to the early operation phases where more accuracy is required and less time to the latter operation phases where less accuracy is required.

REFERENCES:
patent: 3781871 (1973-12-01), Mattern
patent: 3883863 (1975-05-01), Willard
patent: 4893124 (1990-01-01), Tsuji et al.
patent: 4983970 (1991-01-01), O'Donnell
patent: 5059981 (1991-10-01), Hauser
patent: 5212486 (1993-05-01), Nagaraj
patent: 5510789 (1996-04-01), Lee
patent: 5644308 (1997-07-01), Kerth et al.
patent: 5703589 (1997-12-01), Kalthoff et al.
patent: 5786778 (1998-07-01), Adams et al.
patent: 5796358 (1998-08-01), Shih et al.
patent: 5861832 (1999-01-01), Nagaraj
patent: 5875218 (1999-02-01), Barham et al.
patent: 5886562 (1999-03-01), Garrity et al.
patent: 5963160 (1999-10-01), Wilson et al.
patent: 6097326 (2000-08-01), Opris et al.
patent: 6154164 (2000-11-01), Gross, Jr.
patent: 6154165 (2000-11-01), Gross, Jr.
patent: 6195032 (2001-02-01), Watson et al.
patent: 6362835 (2002-03-01), Urbanus et al.
patent: 6486820 (2002-11-01), Allworth et al.
patent: 6501411 (2002-12-01), Soundarapandian et al.
patent: 6535157 (2003-03-01), Garrity et al.
patent: 6541952 (2003-04-01), Nagaraj
patent: 6570519 (2003-05-01), Yang
patent: 6608504 (2003-08-01), Fujimoto
patent: 6680634 (2004-01-01), Ruha et al.
patent: 6700523 (2004-03-01), Konno
patent: 6775345 (2004-08-01), Song
patent: 6794912 (2004-09-01), Hirata et al.
patent: 6826247 (2004-11-01), Elliott et al.
patent: 6909393 (2005-06-01), Atriss et al.
patent: 6927722 (2005-08-01), Hong
Krishnaswami Nagaraj, Senior Member; Efficient Circuit Configurations for Algorithmic Analog to Digital Converters; IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing; Dec. 1993; pp. 1-9; vol. 40, No. 12, no date.

Affiliated with

Also associated with

Rating

Variable clock rate analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable clock rate analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable clock rate analog-to-digital converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3661710