Variable clock dividing circuit

Details Variable clock dividing circuit Variable clock dividing circuit

1992-07-13

1995-02-14

Gaffin, Jeffrey A.

Electrical transmission or interconnection systems

Switching systems

Condition responsive

327115, 327141, H02B 100

Patent

active

053898265

ABSTRACT:
This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.

REFERENCES:
patent: 4500909 (1985-02-01), Machida
patent: 4801875 (1989-01-01), Ige
patent: 5043596 (1991-08-01), Masuda et al.

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